Course Name: EMBEDDED SYSTEMS

Course code: 18EC62

Dr. Suchitra M
Professor
Dept. of ECE, VVCE, Mysuru

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 Syllabus

 Module 1

ARM-32 bit Microcontroller: Thumb-2 technology and applications of ARM,

Architecture of ARM Cortex M3, Various Units in the architecture, Debugging support,
General Purpose Registers, Special Registers, exceptions, interrupts, stack operation,
reset sequence (Text 1: Ch-1, 2, 3)
.

 Module 2

ARM Cortex M3 Instruction Sets and Programming: Assembly basics, Instruction

list and description, Thumb and ARM instructions, Special instructions, Useful
instructions, CMSIS, Assembly and C language Programming (Text 1: Ch-4, Ch-10.1 to
10.6)

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 Contd..
 Module 3

Embedded System Components: Embedded vs General computing system, Classification

of Embedded systems, Major applications and purpose of ES. Elements of an Embedded
System(Block diagram and explanation), Differences between RISC and CISC, Harvard and
Princeton, Big and Little Endian formats, Memory (ROM and RAM types), Sensors,
Actuators, Optocoupler, Communication Interfaces (I2C, SPI, IrDA, Bluetooth, Wi-Fi,
Zigbee only)
(Text2: All the Topics from Ch-1 and Ch-2 (Fig and explanation before 2.1) 2.1.1.6 to
2.1.1.8, 2.2 to 2.2.2.3, 2.3 to 2.3.2, 2.3.3.3, selected topics of 2.4.1
and 2.4.2 only).

 Module 4

Embedded System Design Concepts: Characteristics and Quality Attributes of Embedded

Systems, Operational and non-operational quality attributes, Embedded Systems-
Application and Domain specific, Hardware Software Co- Design and Program Modeling
(excluding UML), Embedded firmware design and development (excluding C language).
Text 2: Ch-3, Ch-4 (4.1, 4.2.1 and 4.2.2 only), Ch-7 (Sections 7.1, 7.2 only), Ch-9
(Sections 9.1, 9.2, 9.3.1, 9.3.2 only)

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 Contd..
 Module 5

RTOS and IDE for Embedded System Design: Operating System basics, Types of
operating systems, Task, process and threads (Only POSIX Threads with an example
program), Thread preemption, Preemptive Task scheduling techniques, Task
Communication, Task synchronization issues — Racing and Deadlock, Concept of Binary
and counting semaphores (Mutex example without any program), How to choose an RTOS,
Integration and testing of Embedded hardware and firmware, Embedded system
Development Environment — Block diagram (excluding Kei1), Disassembler/decompiler,
simulator, emulator and debugging techniques (Text 2: Ch-10 (Sections 10.1, 10.2, 10.3,
10.5.2, 10.7,
10.8.1.1, 10.8.1.2, 10.8.2.2, 10.10 only), Ch-12, Ch-13 (a block diagram before
13.1, 13.3, 13.4, 13.5, 13.6 only

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 Course Outcomes

At the end of this course, students should be able to

1. Describe the architectural features and instructions of 32 bit

microcontroller ARM Cortex M3.
2. Apply the knowledge gained for Programming ARM Cortex M3
for different applications.
3. Analyze the basic hardware components and their selection
method based on the characteristics and attributes of an embedded
system.
4. Develop the hardware software co-design and firmware design
approaches.
5. Explain the need of real time operating system for embedded
system applications.

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 Text Books

1. Joseph Yiu, “ The Definitive Guide to the ARM Cortex-M3”,

second edition, Newness, (Elsevier),2010.

2. Shibu K V, “Introduction to embedded systems”’ Tata

McGraw Hill Education Private Limited, second Edition.

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7 07/10/2021
 Reference Books

8 07/10/2021
 Contd.

No. Activities Planned

1 Quiz

2 Assignment

3 Group activity

4 Module Test

5 Flipped classroom

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 Module 1
ARM 32 bit Microcontroller

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 Introduction

 Digital systems are designed to

store, process, and communicate
information in digital form.
 The digital computer, more
commonly called the computer, is an
example of a typical digital system.
 Logic circuits are used to build
digital systems
 Until 1960’s logic circuits were
constructed with bulky components
such as transistors and resistors.
 With the advent of Integrated
circuits it was possible to place
number of transistors and thus
entire circuit on single chip.
11 07/10/2021
 Contd.

 Integrated circuit (IC), also called microelectronic circuit,

microchip, or chip, is an assembly of electronic components,
fabricated as a single unit.

 It consists of miniaturized active devices and passive

devices, and their interconnections are built up on a thin
substrate of semiconductor material.

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 Contd.

 The integrated circuits are manufactured on a silicon wafer.

 The wafer is cut to produce individual chips.
 They are then placed inside chip package.

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 Advantages

 The entire physical size of IC is extremely small than

that of discrete circuit.
 The weight of an IC is very less as compared entire
discrete circuits.
 It’s more reliable.
 It has lower power consumption.
 Because of less parasitic and capacitance effect it has
increased operating speed.

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 Levels of Integration

SSI:- (10-100) transistors => Example: Logic gates.

MSI:- (100-1000) => Example: counters.

LSI:- (1000-20000) => Example:8-bit chip.

VLSI:- (20000-1000000) => Example:16 & 32 bit chip.

ULSI:- (1000000-10000000) => Example: Special

processors, virtual reality machines, smart sensors.

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 Microprocessor
Is a central processing unit fabricated on a single chip

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Microcontroller

 It is basically a computer on a
single chip.
 Very inexpensive, small, low
power.
 It operates on data that are
fed through its serial or parallel
input ports, controlled by the
software stored in on-chip
memory.
 Often has analog input pins,
timers and other utility
circuitry built-in.

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 Contd.

 Convenient for use in embedded system design.

 Embedded system is a microcontroller-based system
that is designed to control a function or range of
functions, and is not meant to be programmed by the
end user.
 The user may make choices concerning the functionality
but cannot change them.
 The user cannot make modifications to the software.

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 Typical examples

Washing machine,
refrigerator, camera,
vehicles, airplane,
missile, printer

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 How microcontrollers are different from PCs
 When a PC executes a program, the program is first
loaded from disk into an allocated section of memory.
 Operating system handles all low-level operations
 In a microcontroller there is no disk to read from.
 On-chip ROM stores the program that is to be executed.
 Size of the ROM limits the maximum size of the
application.
 There is no operating system, and the program in ROM
is the only program that is running (must include low-
level routines).

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 Advantages of using microcontrollers

 Fast and effective

 Low cost / Low power
 Compatibility

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 Evolution of microcontrollers

 Microcontroller evolved from a microprocessor-based board-

level design to a single chip in the mid-1970's.
 As the process of miniaturization continued, all of the
components needed for a controller were built into a single
chip.
 In the mid-1980’s, microcontrollers got embedded into a
larger ASIC (Application Specific Integrated Circuit).
 Microcontrollers are fabricated as a module inside a larger
chip.

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 Contd.
 The requirement for higher performance
microcontrollers has been driven globally by the
industry’s changing needs.
 Depending on power and features needed

 4 bit
 8 bit
 16 bit
 32 bit microcontrollers

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 History
 ARM was developed at ACRON computer limited of
Cambridge, England between 1983 and 1985

 ARM (Advanced RISC machines) limited was formed in

1990 as, a joint venture of Apple computer, ACRON
computer and VLSI technology.

 Various enhancement made to RISC architecture in

order to fit for embedded applications.

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 Various enhancement made to suit the embedded
applications

 Version 1:
26-bit address bus
No multiply or coprocessor
 Version 2:
26-Bit address bus
Co-processor support
 Version 3:
32-Bit addressing
Faster than ARM version1 and version2

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 Various enhancement made to suit the embedded
applications

 Version 4:
Signed operation support
Thumb instruction set
 Version5:
DSP instructions added
 Version 6:
Memory architecture improved
Thumb2 instruction set

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 Contd .

Version 7:
Thumb2 instruction set
Architecture profiles
ARMv7-A : Application profile
ex: cortex A8
ARMv7-R : Real time profile
ex: cortex R4
ARMv7-M : Microcontroller profile
ex: cortex M3

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 Contd.

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 The Cortex-M3 Processor versus Cortex-M3-
Based MCUs

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 Contd .
 The Cortex-M3 processor is the central processing unit
(CPU) of a microcontroller chip.
 In addition, a number of other components are required
for the whole Cortex-M3 processor-based
microcontroller.
 After chip manufacturers license the Cortex-M3
processor, they can put the Cortex-M3 processor in their
silicon designs, adding memory, peripherals,
input/output (I/O), and other features.
 Cortex-M3 processor-based chips from different
manufacturers will have different memory sizes, types,
peripherals, and features.

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 Contd.

 ARM does not manufacture processors or sell

the chips directly. Instead, ARM licenses the
processor designs to business partners,
including a majority of the world’s leading
semiconductor companies.

 Based on the ARM low-cost and power-

efficient processor designs, these partners
create their processors, microcontrollers, and
system-on-chip solutions.

 This business model is commonly called

intellectual property (IP) licensing

31 07/10/2021
 Contd.
 In 1991, ARM introduced the ARM6 processor ­family,
and VLSI became the initial licensee.
 Subsequently, additional companies, including Texas
Instruments , NEC, Sharp, and ST Microelectronics,
licensed the ARM processor designs.
 Extending the applications of ARM processors into
mobile phones, computer hard disks, personal digital
assistants (PDAs), home entertainment systems, and
many other consumer products.

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33 07/10/2021
34 07/10/2021
Basic Terminologies
Digital computer architectures

Von Neuman Harvard

Architecture Architecture

35 07/10/2021
Contd.

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Contd.

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 Sl Von Neumann
No. architecture
1 Requires single bus for
instructions and data
2 Its design is simpler
3 The Von Neuman
architecture uses single physically separate memories for
memory for their
instructions and data
Harvard
architecture
Requires separate & dedicated
buses for memories for
instructions and data.
Its design is complicated
The Harvard architecture uses
their instructions and data

4 Single bus system Two bus system, a factor that

therefore the design and
makes development of the
development of control
unit is simplified, hence control unit comparatively more
the cost of production expensive.  
becomes minimum.  
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 CPU architectures

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 Cortex M3

40 07/10/2021
Contd.

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Features

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Contd.

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Registers
Registers are the fastest data storage of computing
systems

Processors contains a small set of registers to store

digital values

Each register in cortex M processor is of 32 bits

It has two types of registers

General purpose registers: Stores operands and

intermediate results during the execution of
program.

Special purpose registers: They have predetermined

usage, such as representing the processor status

44 07/10/2021
Contd.

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Contd.
R0–R12 are 32-bit general-purpose registers for data
operations.

R13: Stack Pointers

The Cortex-M3 contains two stack pointers (R13). They are
banked so that only one is visible at a time.

The two stack pointers are as follows:

• Main Stack Pointer (MSP): Processor uses this while

serving interrupts
• Process Stack Pointer (PSP): Processor uses this while
executing regular user programs

R14: Link register

R15: Program Counter

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 R15:
The Program Counter : Holds the memory address of
next instruction that the processor fetches from the
instruction memory.

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 Memory address

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Memory
MEMORY 8 bit
ADDRESS
0x FFFFFFFF  
   
   
   
   
   
0x 00000008  
0x 00000007  
0x 00000006  
0x 00000005  
0x 00000004  
0x 00000003  
0x 00000002  
0x 00000001  
49 0x 00000000   07/10/2021
 R14: The Link Register
When a subroutine is called, the return address
is stored in the link register.

50 07/10/2021
 Contd.

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 Stacks

A stack is a list of data elements (byte or word) with

accessing restriction that elements can be added or
removed at one end only

Fixed amount of space allocated for stack in

memory

The process register called as Stack Pointer(SP) is

used to keep track of the address of the elements of
the stack.

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LIFO (Last In First Out)

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54 07/10/2021
 Stack Operations
PUSH {R1}
POP {R1}
R1= 4567abcd
SP
SP+4 10
10
0F 45 0F 45
0E 67 0E
67
SP-4 0D ab 0D ab
SP
0C cd 0C cd
0B 0B
0A 0A
09 09

R1= 4567abcd

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56 07/10/2021
 PUSH and POP of individual registers
Branch with BX LR

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 PUSH and POP of group of registers
Branch with BX LR

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59 07/10/2021
 Branch without BX LR

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 Special registers

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 Program status register

PSR is a combination of three register.

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Condition Codes

The processor keeps track of information about the results various

operations.
This is accomplished by recording the required information in
individual bits often called condition code flags.
These flags are usually grouped together in a special purpose
register called the condition code register or status register.
Four commonly used flags are
N(Negative) set to 1 if the result is negative; otherwise cleared to
0
Z(Zero) set to 1 if the result is 0; otherwise , cleared to 0
V(Overflow) set to 1 if arithmetic overflow occurs otherwise
cleared to 0
C(Carry) Set to 1 if a carry-out results from the operation;
otherwise, cleared to 0
Q= set to indicate saturation, used for DSP related instruction

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64
07/10/2021
 Contd.

65

07/10/2021
 Consider two numbers 0xFFFF FFFE and 0×0000 0002.
A 32-bit mathematical addition would result in 0×1 0000
0001 which contain 9 hex digits or 33 binary bits.

Saturate arithmetic says that when the result crosses the

extreme limit the value should be maintained at the
respective maximum/minimum

Saturate instructions are very useful in implementing certain

DSP algorithms like audio processing where we have a cutoff
high in the amplitude.

For instance the highest amplitude is expressed by a 32-bit

value and if audio filter gives an output more than this, need
not programmatically monitor the result. Rather the value
automatically saturates to the max limit.

Also a new flag field called ‘Q’ has been added to the ARM
processor to show us if there had been any such saturation
taken place.
66 07/10/2021
 Contd.

ICI/IT bits hold the state information for IT block instructions or

instructions that are suspended during interrupt processing.

When an interrupt occurs during the execution of

an LDM, STM, PUSH, or POP instruction, the processor:
stops the load multiple or store multiple instruction operation
temporarily stores the next register operand in the multiple
operation to EPSR bits.

After servicing the interrupt, the processor:

returns to the register pointed to by bits
resumes execution of the multiple load or store instruction.

T=1, executing thumb instructions

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 Contd.

The LSB 9 bits indicate the interrupt number

It is all zeros if not executing any interrupts

Control register
Define privileged status and stack pointer selection

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Special registers for interrupt masking
purpose
Contd.

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71 07/10/2021
 Contd.

The PRIMASK register is used to disable all exceptions except

NMI and hard fault
In C programming, the intrinsic functions provided in Cortex
Microcontroller Software Interface Standard (CMSIS)
compliant device driver libraries are provided in the compiler
to set and clear PRIMASK:
void __enable_irq(); // Clear PRIMASK
void __disable_irq(); // Set PRIMASK

MOV R0, #1
MSR PRIMASK, R0 ; Write 1 to PRIMASK to disable all
interrupts and
MOV R0, #0
MSR PRIMASK, R0 ; Write 0 to PRIMASK to allow interrupts

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 Contd.
To disable interrupts only with priority lower than a certain level.
the value is written to BASEPRI:

_ set_BASEPRI(0x60); // Disable interrupts with priority 0x60-

0xFF using CMSIS Or in assembly language:
MOV R0, #0x60;
MSR BASEPRI, R0 ;

To read back the value of BASEPRI:

x = __get_BASEPRI(void); // Read value of BASEPRI
Or in assembly language:
MRS R0, BASEPRI ;

To cancel the masking, just write 0 to the BASEPRI register:

__set_BASEPRI(0x0); // Turn off BASEPRI masking
Or in assembly language:
MOV R0, #0x0
MSR BASEPRI, R0 ;
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 Interrupts

74 07/10/2021
Contd.

 The Cortex-M3 provides a feature-

packed exception architecture that
supports a number of system exceptions
and external interrupts commonly called
IRQ .
 Exceptions are the interrupts that come
from processor core
 Interrupts deals with external activities
of peripherals such as push buttons,
keypads
 These are used to inform the
microcontroller of external events
efficiently
 Contd.

Exceptions are numbered 1-15 for system exceptions

and 16 and above for external interrupt inputs.

Most of the exceptions have programmable priority,

and a few have fixed priority.

The number of interrupt inputs on a Cortex-M3

microcontroller depends on the individual design. The
typical number of interrupt inputs is 16 or 32.

Priority determines the order of interrupts to be

serviced

A lower value of priority number represents higher

priority

76 07/10/2021
Contd.

77 07/10/2021
 Contd.

 When an exception event takes place on the

Cortex-M3 and is accepted by the processor core,
the corresponding exception handler is executed.
(interrupt, ISR)

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Multiple interrupts
Contd.
Contd.
 The interrupt controller in Cortex M3 processor is called the
Nested Vectored Interrupt Controller (NVIC)
 It is built in to cortex core to manage all interrupts

 Features

 Vectored interrupt support

 Nested interrupt support
 Interrupt masking
 Reduction of interrupt latency
 Vector Table

 When an exception event takes place on the

Cortex-M3 and is accepted by the processor core,
the corresponding exception handler is executed.
(interrupt, ISR)

 To determine the starting address of the exception

handler, a vector table mechanism is used.

 The vector table is an array of word data inside the

system memory, each representing the starting
address of one exception type.

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Servicing multiple interrupts
Vector Table

84 07/10/2021
 Contd.

 For example, if the reset is exception type 1, the

address of the reset vector is 1 times 4 (each word is 4
bytes), which equals 0x00000004,
 and NMI vector (type 2) is located in 2 × 4 =
0x00000008.
 The address 0x00000000 is used to store the starting
value for the MSP
 The vector table is relocatable, and the relocation is
controlled by a relocation register in the NVIC

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Automated nested interrupt handling
 Contd.

The NVIC provides nested interrupt support.

All the external interrupts and most of the system exceptions

can be programmed to different priority levels.

When an interrupt occurs, the NVIC compares the priority of

this interrupt to the current running priority level.

If the priority of the new interrupt is higher than the current

level, the interrupt handler of the new interrupt will override the
current running task.

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 Interrupt Latency

 The term interrupt latency refers to the delay from the

start of the interrupt request to the start of interrupt
handler execution

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 Interrupt Latency

 The Cortex-M3 processor also includes a number of

advanced features to lower the interrupt latency.
 Allows exceptions in the middle of Multiple Load and
Store instructions (LDM/STM).
 Reducing delay in switching from one ISR to another
 Handling of late arrival interrupts

89 07/10/2021
 Contd.
 When an exception takes place but the processor is
handling another exception of the same or higher
priority, the exception will enter pending state.
 Instead of restoring the registers back from the stack
(unstacking) and then pushing them onto the stack
again (stacking),
 the processor skips the unstacking and stacking steps
and enters the exception handler of the pended
exception as soon as possible.
 In this way, the timing gap between the two exception
handlers is considerably reduced

90 07/10/2021
 Contd.

 Another feature that improves interrupt performance is

late arrival exception handling.
 When an exception takes place and the processor has
started the stacking process, and if during this delay a
new exception arrives with higher preemption priority,
the late arrival exception will be processed first

91 07/10/2021
Contd.

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 Exception No. 1

 Reset
 Fixed priority level of -3
 Indicates higher priority
 Power on or system Reset
 Asserted when the device is powered up; resets
processor core, peripherals, and debugging system

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 Exception No. 2
Nonmaskable interrupt (NMI)

Fixed priority level of -2

Cannot be stopped or preempted

by any exception other than reset

The actual use of NMI depends on

the design of the microcontroller

In most cases, the NMI could be

connected to a watchdog timer or
a voltage-monitoring block that
warns the processor when the
voltage drops below a certain level

The NMI exception can be

activated any time
 Contd.

A number of system exceptions are

useful for fault handling.

There are several categories of

faults:

• Bus faults
• Memory management faults
• Usage faults
• Hard fault

95 07/10/2021
Contd.

 Memory Management Fault

 Exception No. 4
 Memory Protection Unit (MPU) violation or access to illegal
locations
Access to memory regions not defined in MPU setup
• Writing to read-only regions
• An access in the user state to a region defined as privileged
access

96 07/10/2021
Contd.
 Bus fault
 Exception No. 5
 Attempts to access an invalid memory region (for example, a
memory location with no memory attached) •
 The device is not ready to accept a transfer (for example,
trying to access SDRAM without initializing the SDRAM
controller)
 Attempts to carry out a transfer with a transfer size not
supported by the target device (for example, doing a byte
access to a peripheral register that must be accessed as a
word)

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  Usage Faults
Exception No. 6
Undefined instructions
Invalid interrupt return
(link register contains invalid/incorrect values)
Divide by zero

Hard Faults
Exception No. 3
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or masked
by exception masking

98 07/10/2021
Contd.

 The exception handler is a program that can inform the

programmer where in his or her code this exception has
occurred (after the application has crashed).
 The exception handler ought to handle the consequences of
the aborted instruction gracefully, rather than forcing the
processor to hang in an infinite loop.

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 Supervisor call

Exception No. 11

SVC is for generating system function calls.

For example, instead of allowing user programs to directly

access hardware, an operating system may provide access
to hardware through an SVC.

So when a user program wants to use certain hardware,

it generates the SVC exception using SVC instructions,
and then the software exception handler in the operating system
is executed and provides the service the user application requested.

In this way, access to hardware is under the control of the OS,

which can provide a more robust system by preventing
the user applications from directly accessing the hardware

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  System tick timer
 Exception No. 15
 24 bit down counter
 Counts down from an initialize
value

Used to initialize a action on periodic basis

When multiple tasks run concurrently, processor allocates

time slots to each task

To achieve this processor uses system tick timer which

inturn inform the task to stop the current task and takeup
another in the queue

101 07/10/2021
 Contd.

 PendSV - Pendable request for system service.

Exception type 14
 Debug monitor is exception type 12
and its priority is programmable. It can be invoked by
means of debug events, as well as by manually setting the
pending bit.
After debugging is completed, the program execution can
be returned to normal by carrying out an exception return.

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 HAPPY
LEARNING


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