LIC Unit I

UNIT
1 IC Fabrication
IC classification, fundamental of monolithic IC technology,

epitaxial growth, masking and etching, diffusion of
impurities. Realisation of monolithic ICs and packaging.
Fabrication of diodes, capacitance, resistance, FETs and PV
Cell.
Integrated Circuits (ICs)
An integrated circuit (IC) is a miniature, low cost electronic circuit consisting of active and passive components
fabricated together on a single crystal of silicon. The active components are transistors and diodes and passive
components are resistors and capacitors.
Advantages:
• Miniaturization and hence increased equipment density.
• Cost reduction due to batch processing.
• Increased system reliability due to the elimination of soldered joints.
• Improved functional performance.
• Increased operating speeds.
• Reduction in power consumption. Matched devices.
Limitations:
• Limited power rating. It operates at low voltage.
• High grade of PNP is not possible.
• It produces noise during operation.
• Its components such as resistors and capacitors are voltage dependent.
• It is delicate i.e., it cannot withstand rough handling etc.
IC - Classification
ICs can be classified on the basis of their chip size as given below:
• Small Scale Integration (SSI)—3 to 30 gates/chip or 100 transistors/chip (logic gate, flip-flops).
• Medium Scale Integration (MSI)—30 to 300 gates/chip or 100 to 1000 transistors/chip (counters, mux, adders).
• Large Scale Integration (LSI)—300 to 3,000 gates/chip or 1000 to 20,000 transistors/chip (8bit MP, ROM, RAM).
• Very Large Scale Integration (VLSI)—more than 3,000 gates/chip or 20,000 to 10,00,000 transistors/chip (16/32 MP).
Types of ICs:
Based on the method or techniques used in manufacturing them, types of ICs can be divided into three classes:
1. Thin and thick film ICs: In thin or thick film ICs, passive components such as resistors,
capacitors are integrated but the diodes and transistors are connected as separate components to
form a single and a complete circuit. Thin and thick ICs that are produced commercially are merely
the combination of integrated and discrete (separate) components.
2. Monolithic ICs: All circuit components, both active and passive elements and their
interconnections are manufactured into a single silicon chip.
Types: 1. Bipolar:- i) PN Junction isolation ii) Dielectric isolation.
2. Unipolar:- i) MOSFET ii) JFET.
3. Hybrid or Multichip ICs: It is a miniaturized electronic circuit constructed of individual

devices, such as semiconductor devices (e.g. transistors, diodes and/or monolithic ICs) and passive
components (e.g. resistors, inductors, transformers, and capacitors), bonded to a substrate or printed
circuit board (PCB).
Monolithic IC Technology
Monolithic IC Manufacturing Process. For the manufacture and production of the monolithic
IC, all circuit components and their interconnections are to be formed in a single thin wafer.
The different processes carried out for achieving this are explained below.
The basic processes involved in the fabrication of ICs are as follows:

1. Silicon wafer preparation.
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Isolation Techniques
8. Metallization
9. Assembly Processing and packaging.
1. Silicon Wafer preparation:
The following steps are involved in the preparation of Si-wafers:
i. Crystal growth and doping
ii. Ingot trimming and grinding
iii. Ingot slicing
iv. Wafer polishing and etching
v. Wafer cleaning
i. Crystal growth and doping:
• The starting material for crystal growth is highly purified polycrystalline silicon.
• The primary method of the crystal growth is the Czochralski method.
• The apparatus used for the crystal growth is called as Czochralski crystal growth
apparatus or puller.
• The puller has 4 important subsystems namely furnace, crystal puling mechanism,
ambient control and control systems. The simplified version of Czochralski crystal puller
is shown in figure:
ii. Ingot Trimming and grinding:
• First the seed which initiated the crystal growth is separated from the circular ingot. The top
and bottom ends are cut off. As silicon is hard and brittle material, industrial grade diamond
is used for shaping and cutting it. This process is called as ingot trimming.
• After trimming of the ingot, the surface grinding of the ingot is carried out.
• Two flats are ground along the length of the ingot .The larger flat is called as major or
primary flat and it is positioned relative to the crystal direction. The smaller flat is called as
secondary flat.
• The X-ray technique is used to locate the primary flat.
• The primary flat is very important as
• It serves for mechanical alignment of the wafer in automatic processing.
• It serves for orienting ICs on the wafer relative to the crystal.
iii. Ingot Slicing:
• The slices of the ingot are called as wafers. And the thickness of wafers may vary from 0.4 mm to 1 mm.
• The ingot is sliced using a circular cutting blade kept in tension on the outer edge while having the cutting
edge on the inner diameter. The thickness of the wafer is determined by the slicing.
iv. Wafer polishing and etching:
• Due to trimming, grinding and slicing the surface and edges to the wafers get contaminated and even damaged.
• Practically mixture of hydrofluoric acid and nitric acid is used in chemical etching. This is called as acidic
etching.
• The other alternative is to use alkaline etching using potassium hydroxide or sodium hydroxide.
• After etching, the wafer is polished to eliminate the micro-cracks and debris. The main intension of polishing a
wafer is to provide a smooth and perfect flat surface.
• The polishing is done with the help of polishing machine. The three steps of lapping, etching and polishing
reduce the wafer thickness by 40 to 150 µm.
v. Wafer cleaning:
• The silicon wafers are cleaned using chemicals. Generally organic films, heavy metals, are deposited on the
surface of the wafers. First the wafer is cleaned by using hydrochloric acid and then the wafer is rinsed in
water to deionize. Again the wafer is dipped in hydrofluoric acid.
2. Epitaxial Growth:
2. Epitaxial Growth:
• The word epitaxy is derived from Greek word epi meaning 'upon' and the past tense of the
word teinon meaning 'arranged'. So, the epitaxy can be described as, arranging atoms in single
crystal fashion upon a single crystal substrate.
• The basic chemical reaction used for the epitaxial growth of pure silicon is the hydrogen
reduction of silicon tetrachloride.
• The epitaxial films with specific impurity concentration are accomplished by introducing
phosphine (PH3) for the n-type and bi-borane (B2H6) for p-type doping into the silicon-
tetrachloride hydrogen gas stream.
• The process is carried out in a reaction chamber consisting of a long cylindrical quartz tube
encircled by an RF induction coil.
• The silicon wafers are placed on a rectangular graphite rod called a boat. This boat is then
placed in the reaction chamber where the graphite is heated inductively to a temperature
1200°C. The various gases required for the growth of desired epitaxial layers are introduced
into the system through a control console.
3. Oxidation:
• The process in which a thin layer of silicon dioxide (SiO2) formed on the surface of
silicon wafer using thermal growth technique is called Oxidation.
• Si02 serves two very important purposes.
1. Si02 is an extremely hard protective coating and is unaffected by almost all reagents
except hydrofluoric acid.
2. By selective etching, diffusion of impurities through carefully defined windows in the
Si02 can be accomplished to fabricate various components.
• The silicon wafers are stacked up in a quartz boat and then inserted into quartz furnace
tube. The Si-wafers are raised to a high temperature in the range of 950 to 1115°C and at
the same time, exposed to a gas containing O2 or H20 or both. The chemical reaction is Si
+ 2H20 Si02 + 2H2
• This oxidation process is called thermal oxidation because high temperature is used to
grow the oxide layer. The thickness of the film is governed by time, temperature and the
moisture content. The thickness of oxide layer is usually in the order of 0.02 to 2 µm.
4. Photolithography:
• Photolithography is the process of transferring geometric shapes on a mask to the surface of a silicon wafer.
• The Photolithography involves - two processes, namely:
i) Making of a photographic mask and ii) Photo etching.
i. Making of a photographic mask
The making of a photographic mask involves the following sequence of operations
• First the preparation of initial artwork and secondly, its reduction.
• The initial layout or artwork of an IC is normally done at a scale several hundred times larger than the final
dimensions of the finished monolithic circuit. This is because, for a tiny chip, larger the artwork, more accurate is
the final mask.
• This initial layout is then decomposed into several mask layers, each corresponding to a process step in the
fabrication schedule, e.g., a mask for base diffusion, another for collector diffusion, another for metallization and
so on.
• The artwork is usually produced on a precision drafting machine, known as coordinatograph. The
coordinatograph has a cutting head that can be positioned accurately and moved along two perpendicular axes.
The coordinatograph outlines the pattern cutting through the red mylar without damaging the clear layer
underneath.
• This rubylith pattern of individual mask is photographed and then reduced in steps by a factor of 5 or 10 several
times to finally obtain the exact image size. The final image also must be repeated many times in a matrix array,
so that many ICs will be produced in one process.
ii. Photo etching
• Photo-etching is used for the removal of Si02 from desired regions so that the desired impurities can be diffused.
• The wafer is coated with a film of photosensitive emulsion (Kodak Photoresist KPR).
• The thickness of the film is in the range of 5000-10000 A as shown in Fig.(a).
• The mask negative of the desired
pattern) as prepared by steps described
earlier is placed over the photoresist
coated wafer as shown in Fig.(b). This is
now exposed to ultraviolet light, so that
KPR becomes polymerized beneath the
transparent regions of the mask. The
mask is then removed and the wafer is
developed using a chemical
(trichloroethylene) which dissolves the
unexposed/unpolymerized regions on the
photoresist and leaves the pattern as
shown in Fig. (c).
ii. Photo etching
• The polymerized photoresist is next fixed or cured, so that it becomes immune to certain
chemicals called etchants used in subsequent processing steps.
• The chip is immersed in the etching solution of hydrofluoric acid, which removes the Si0 2
from the areas which are not protected by KPR as shown in Fig.(d).
• The etching process described is a wet etching process and the chemical reagents used are in
liquid form. A new process used these days is a dry etching process called plasma etching.
• A major advantage of the dry etching process is that it is possible to achieve smaller line
openings compared to wet process.
5. Diffusion:
• The process of doping or adding impurity to the silicon wafer is called as
diffusion.
• Diffusion is used to form bases, emitters and resistors in bipolar device.
• This uses a high temperature furnace having a flat temperature profile over a
useful length (about 20" length).
5. Diffusion:
• A quartz boat containing about 20 cleaned wafers is pushed into the hot zone
with temperature maintained at about a 1000°C.
• Impurities to be diffused are rarely used in their elemental forms. Normally,
compounds such as B203 (Boron oxide), BCl3 (Boron chloride) are used for
Boron and P205 (Phosphorous pentaoxide) and POCl3 (Phosphorous
oxychloride) are used as sources of Phosphorous.
• A carrier gas, such as dry oxygen or nitrogen is normally used for sweeping the
impurity to the high temperature zone.
• The depth of diffusion depends upon the time of diffusion which normally
extends to 2 hours.
• The diffusion of impurities normally takes place both laterally as well as
vertically. Therefore, the actual junction profiles will be curved as shown in the
following Fig.
6. Ion Implantation:
This is another technique used to introduce impurities into a silicon wafer. In this process, silicon wafers are
placed in a vacuum chamber and are scanned by a beam of high energy dopant ions (borons for p-type and
phosphorus for n-type). These ions are accelerated by energies between 20 kV to 250 kV. As the ions strike
the silicon wafers, they penetrate some small distance into the wafer. The depth of penetration of any
particular type of ion increases with increasing accelerating voltage.
It has two main advantages:

1. It is performed at low temperature.
2. In Ion implantation process, accelerating
potential and the beam current are electrically
controlled from outside.
The main blocks of the ion-implanter are ion source,
bending analyzer magnet, aperture, acceleration
tube, X-Y scanner plates, target chamber.
The bending analyzer magnet selects the ions with
desired charge to mass ratio with the help of
properly applied magnetic field.
7. Isolation Techniques:
The most commonly used isolation techniques are:
i. p-n junction isolation
ii. Dielectric isolation
i. p-n junction isolation

• In this isolation technique, p+ type impurities are selectively diffused into the n-type epitaxial
layer so as to reach p-type substrate as shown in Fig.
• This produces islands surrounded by p-type moats. It can be seen that these regions are
separated by two back-to-back p-n junction diodes.
• If the p-type substrate material is held at the most negative potential in the circuit, the diodes
will be reverse biased providing electric isolation between these islands. The different
components are fabricated in these isolation islands.
7. Isolation Techniques:
ii. Dielectric isolation
• Here a layer of solid dielectric such as silicon dioxide or ruby completely surrounds each
component, thereby producing isolation, both electrical and physical.
• This isolating dielectric layer is thick enough so that its associated capacitance is negligible.
Also, it is possible to fabricate both PNP and NPN transistor within the same silicon substrate.
• Since this method requires additional

fabrication steps, it becomes more expensive.
• This technique is mostly used for fabricating
professional grade ICs required for
specialised applications viz, aerospace and
military, where higher cost is justified by
superior performance.
8. Metallization:
• The purpose of this process is to produce a thin metal film layer that will serve to make
interconnections of the various components on the chip. Aluminium is usually used for the
metallization of most lCs as it offers several advantages.
The advantages are as follows:
• It is relatively a good conductor (Aluminium)
• Aluminium makes good mechanical bonds with silicon.
• It forms low-resistance and so it is used for metallization.
Metallization process:
• The process takes place in a chamber which is called as vacuum evaporation
chamber.
• The chamber pressure is adjusted to range 10-6 to 10-7 Torr. The material to be
evaporated is placed in a basket.
• Then using electron gun high power density electron beam is focused at the
surface of the material.
• After the metallization process is over, the thin film is patterned to form required
interconnections.
• By using proper etching process aluminium is removed from unwanted regions.
9. Assembly processing and packaging:
• Each chip is then mounted on a ceramic wafer and attached to a suitable package.
There are 3 different package configurations available:
1. Metal can package.
2. Ceramic flat package.
3. Dual –in-line type.
The metal can packages are available in 8, 10 or

12 leads, whereas the flat or dual-in-line
package is commonly available in 8, 14 or 16
leads, but even 24 or 36 or 42 leads are also
available for special circuits.
Ceramic packages, whether of flat type or dual-
in-line are costly due to fabrication process, but
have the advantage of best hermetic sealing.
Fabrication of Circuit Step-1: Wafer Preparation: The starting material called the substrate is
a p-type silicon wafer
The wafers are usually of 10-cm diameter and 0.4 mm (~ 400 mm)
thickness.
Step-2: Epitaxial Growth: An n-type epitaxial film (5–25 mm) is grown on the p-type
substrate
This ultimately becomes the collector region of the transistor, or an element of the diode and
diffused capacitor associated with the circuit. So, in general it can be said that all active and
passive components are fabricated within this layer.
The resistivity of n-epitaxial layer is of the order of 0.1 to 0.5 Ω-cm.
Fabrication of Circuit Step-3: Oxidation: A SiO2 layer of thickness of the order of 0.02 to 2 mm is
grown on the n-epitaxial layer.
Step-4: Isolation Diffusion

Four components have to be fabricated, so we require four islands which are isolated. For this, SiO2 is removed
from five different places using photolithographic technique. As long as the pn junctions between the isolation
islands are held at reverse bias, that is, the p-type substrate is held at a negative potential with respect to the n-type
isolation islands, these regions are electrically isolated from each other by two back-to-back diodes, providing the
desired isolation.
Fabrication of Circuit Step-5: Base Diffusion: A new layer of SiO2 is grown over the entire
wafer and a new pattern of openings is formed using photolithographic
technique. Now, p-type impurities, such as boron, are diffused through
the openings into the islands of n-type epitaxial silicon. The depth of
this diffusion must be controlled so that it does not penetrate through n-
layer into the substrate. This diffusion is utilized to form base region, of
the transistor, resistor, the anode of the diode and junction capacitor.
Fabrication of Circuit Step-6: Emitter Diffusion: A new layer of SiO2 is again grown over
the entire wafer and selectively etched to open a new set of windows
and n-type impurity (phosphorus) is diffused through them. This forms
transistor emitter and cathode region of diode Windows (W1, W2 etc.)
are also etched into n-region where contact is to be made to the n-type
layer. Heavy concentration of phosphorus (n+) is diffused into these
regions simultaneously with the emitter diffusion. Aluminium,
normally used for making interconnections, is a p-type impurity in
silicon, and can produce an unwanted rectifying contact with the
lightly-doped n-material.
Fabrication of Circuit
Step-7: Aluminium Metalization
An aluminium layer is used for obtaining interconnection
between components (~ 1mm).
Fabrication of Circuit Monolithic IC Technology
Component Fabrication : Transistors
• The fabrication process of a transistor is shown in the figure below. A P-type substrate is first grown and then the
collector, emitter, and base regions are diffused on top of it as shown in the figure. The surface terminals for these
regions are also provided for connection.
• Both transistors and diodes are fabricated by using the epitaxial planar diffusion process. In case of discrete
transistors, the P-type substrate is considered as the collector. `But this is not possible in monolithic IC’s, as all the
transistors connected on one P-type substrate would have their collectors connected together. This is why separate
collector regions are diffused into the substrate. Even though separate collector regions are formed, they are not
completely isolated from the substrate. For proper functioning of the circuit it is necessary that the P-type substrate
is always kept negative with respect to the transistor collector. This is achieved by connecting the substrate to the
most negative terminal of the circuit supply.
The unwanted or parasitic junctions, even when reverse-
biased, can still affect the circuit performance adversely. The
junction reverse leakage current can cause a serious problem
in circuits operating at very low current levels. The
capacitance of the reverse-biased junction may affect the
circuit high-frequency performance, and the junction break
down voltage imposes limits on the usable level of supply
voltage. All these adverse effects can be reduced to the
minimum if highly resistive material is employed for the
substrate. If the substrate is very lightly doped, it will behave
Component Fabrication : Diodes
• They are also fabricated by the same diffusion process as transistors, the only
difference is that only two of the regions are used to form one P-N junction. In
figure, collector-base junction of the transistor is used as a diode. Anode of the
diode is formed during the base diffusion of the transistor and the collector
region of the transistor becomes the cathode of the diode. For high speed
switching emitter base junction is used as a diode.
Component Fabrication : Resistors
The resistors used in IC’s are given their respective ohmic value by varying the concentration of doping
impurity and depth of diffusion. The range of resistor values that may be produced by the diffusion
process varies from ohms to hundreds of kilohms. The typical tolerance, however, may be no better than
± 5%, and may even be as high as ± 20%. On the other hand, if all the resistors are diffused at the same
time, then the tolerance ratio may be good. Most resistors are formed during the base diffusion of the
integrated transistor, as shown in figure below. This is because it is the highest resistivity region. For low
resistance values, emitter region is used as it has much lower resistivity.
Another diffusion technique is also used for the

growth of IC resistors. It is basically a thin-film
technique. In this process a metal film is
deposited on a glass or Si02 surface. The
resistance value can be controlled by varying
thickness, width and length of the film. Since
diffused resistors can be processed while
diffusing transistors. This technique is more
economic and less time consuming and therefore,
the most widely used.
Component Fabrication : Capacitors
• The figure below shows the P and N-regions forming the capacitor plates. The dielectric of the
capacitor is the depletion region between them. All P-N junctions have capacitance so capacitors may
be produced by fabricating junctions. The amount of change in the reverse bias varies the value of
junction capacitance and also the depletion width. The value may be as less as 100 picoFarads.
• Using the silicon dioxide as a dielectric may also be a way to fabricate capacitors. One plate of the
capacitors is formed by diffusing a heavily doped N-region. The other plate of the capacitor is formed
by depositing a film of aluminium on the silicon dioxide dielectric on the wafer surface. For such a
capacitor, a voltage of any polarity can be used, and when comparing a diffused capacitor with such a
capacitor the diffused capacitor may have very small values of breakdown voltage.
Diode Fabrication:
They are also fabricated by the same
diffusion process as transistors are. The
only difference is that only two of the
regions are used to form one P-N
junction. In figure, collector-base junction
of the transistor is used as a diode. Anode
of the diode is formed during the base
diffusion of the transistor and the
collector region of the transistor becomes
the cathode of the diode. For high speed
switching emitter base junction is used as
a diode.
Transistor Fabrication:
In PN junction isolation technique, the P+ type impurities are selectively diffused into the N-type epitaxial layer
so that it touches the P-type substrate at the bottom. This method generated N-type isolation regions surrounded
by P-type moats. If the P-substrate is held at the most negative potential, the diodes will become reverse-biased,
thus providing isolation between these islands. The individual components are fabricated inside these islands.
This method is very economical, and is the most commonly used isolation method for general purpose integrated
circuits.
Fabrication of Diodes, Capacitors, Resistors
Semiconductor Fabrication:
a) The mono-crystal silicon wafer is polished in order to obtain a substrate with its surface as regular and flat as
possible.
b) The top of the wafer is then prepared for photolithography by covering it with an insulating layer to serve as a
mask, typically an oxide,
c) And a subsequent covering film of protective material which is sensitive to light, called photoresist.
d) A photo mask with the circuit pattern for one layer of the chip is loaded and aligned with the wafer.
e) The exposure process of the wafer to intense UV light through the mask allows to remove the exposed
photoresist area.
f) The unprotected insulating material is then striped away using a chemical etching process and the remaining
photoresist is removed by a developer solution.
g) In general, there are two types of photoresist: negative and positive. When exposed to UV light, the negative
photoresist becomes polymerized and more difficult to dissolve in developer solution than the positive resist.
For negative resist, the developer solution removes only the unexposed areas. In this way, it is possible to create
a pattern of non-protected silicon wafer areas surrounded by regions of non-conducting material. Then, the
modification of the electrical properties of the exposed areas involves doping processes, such as ion
implantation which is used to create sources and drains of the transistor.
Other conducting or insulating layers may also be added. A new layer of material is added and the entire
photolithography process, which includes imaging, deposition, etching, and doping, is repeated to create many
different components of the chip, layer by layer.
Once all the components of the
IC are ready, the processing
step is performed to deposit the
metal wiring between the
individual devices in order to
interconnect them, with a
process called metallization.
Common metals used in the
semiconductor industry are
copper and aluminum, but
recently many other metals are
being tested for applicability
for metal interconnects at the
nano-scale.
a) The second stage of the chip fabrication also includes the formation of contacts and dielectric
structures.
b) When the first layer of a conducting metal is deposited on top of the wafer.
c) A layer of UV-sensitive photoresist is added on the top of the metal. Then, in a manner similar to the
processing of the components during the FEOL processing, a UV-light source is exposed to the
photoresist through a mask describing the desired layout of the metal wires; the exposed section of
the positive photoresist is then removed in the subsequent chemical etching step.
d) The etching process eliminates the unprotected metal to obtain a pattern of wires described by the
mask which connects the different components of the chip.
e) Most ICs need more than one layer of wires to form all the necessary connections. In real chips, as
many as 5-12 layers are added in the process. Typically, metal interconnecting wires are isolated by
dielectric layers to prevent the wires from creating a short circuit with other metal layers. The
various metal layers are interconnected by etching holes, called vias, in the insulating material.
After the processing, the post-fab process is performed, which includes wafer testing, die separation, die
testing, IC packaging, and final device testing.

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UNIT

IC classification, fundamental of monolithic IC technology,

3. Hybrid or Multichip ICs: It is a miniaturized electronic circuit constructed of individual

The basic processes involved in the fabrication of ICs are as follows:

It has two main advantages:

i. p-n junction isolation

• Since this method requires additional

The metal can packages are available in 8, 10 or

Step-4: Isolation Diffusion

Another diffusion technique is also used for the

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