VHDL AES 128

Encryption/Decryption
Bradley University
Department of Electrical and
Computer Engineering

Senior Capstone Project

Advisor: Dr. Vinod Prasad

David Leifker
Gentre Graham

April 7th 2005

 Presentation Outline

 Project Introduction
 Functional Description
 Difficulties & Solutions
 Simulation, Verification, & Demonstration
 Conclusion
 Project Introduction: AES
 AES (Advanced Encryption Standard)
 Key Lengths 128,192,256 bits (FIPS 197)
 Block Cipher
 Approved by NSA (National Security Agency)
 Plain Text
 Unencrypted Data
 Cipher Text
 Encrypted Data
 Encryption Key (Secret Key)
 Enables conversion between Cipher Text & Plain Text
 Project Introduction

 VHDL (Very High Speed Integrated

Circuit Hardware Description Language)

 FPGA (Field-Programmable Gate Array)

 HID ( Human Interface Device)

 PS/2 Keyboard
 LCD ( Liquid Crystal Display )
 Project Introduction:
Applications
 Secure Communication
 ATM
 DVD Content
 Secure Networks
 Secure Storage
 Confidential Corporate Documents
 Government Documents
 FBI Files
 Personal Storage Devices
 Person Information Protection
 Project Introduction:
Hardware

 PC with Xilinx ISE 6.31i

 NU Horizons
 Xilinx Spartan III Development
Board
 XCS400-4 PQ208C
 PS/2 Input
 4 x 20 Line LCD Display
 Presentation Outline

 Project Introduction

 Functional Description
 Difficulties & Solutions
 Simulation, Verification, &
Demonstration
 Conclusion
Functional Description
Sub-System Block Diagram
Program PS2
Control Keyboard
Logic Interface
180 LoC 719 LoC

AES Core
RAM
51 LoC
1254 LoC
LCD
ROM Misc. LoC: 290 Interface

67 LoC 440 LoC

Total Lines of Code ≈ 3000

Sub-System Block Diagram
 Inside The AES Core
Key Expansion Encryption Decryption

MixColumns Inverse
Rcon MixColumns

Shift Rows Inverse

Shift Rows

Inverse
Substitute Byte
Substitute Byte

Add Round Key

 Inside The AES Core
Current State Key Schedule Next State

Add Round Key

 Inside The AES Core
Current State Next State

256 Byte
Array

Substitute Byte & Inverse

 Inside The AES Core

Current State Next State

Shift Rows & Inverse

 Inside The AES Core

Next State Current State

MixColumns
 Inside The AES Core

Next State Current State

Inverse MixColumns
 Presentation Outline

 Project Introduction
 Functional Description

 Difficulties & Solutions

 Simulation, Verification, &
Demonstration
 Conclusion
 Difficulties & Solutions
 Development Board PS/2 Port
 Replaced with External PS/2 Port
 Development Board Documentation Did Not
Reflect Board Specifications
 Clock Speed
 LCD Character Addressing (4x24 vs 4x20)
 LCD Timing
 Test Bench Development
 Area Constraints of the FPGA
 Hard Coded Encryption Key
 Reduction of States by Looping (LCD)
 Presentation Outline

 Simulation, Verification, &

Demonstration
 FIPS 197 Documented Example
 ModelSim Computer Simulation
 FPGA Demonstration
Demonstration: FIPS 197
Demonstration: Encryption
Demonstration: Decryption
Demonstration: Encryption
ModelSim Computer Simulation
Demonstration: Decryption
ModelSim Computer Simulation
Software Flow Chart
Demonstration: Splash Screen
Demonstration: ASCII Input
Demonstration: ASCII Input
Demonstration: ASCII Input
Demonstration: HEX Input
Demonstration: Encryption
Demonstration: Decryption
Improvements & Additions

 Larger LCD Display

 192 or 256 Bit level Encryption
 High Speed Mode
 PC Integration
Questions?