COMPUTER ORGANIZATION

UNIT-4
Basic Structure of Computers
 What is a computer?
 A computer is an electronic device that manipulates
information, or data. It has the ability to store, retrieve,
and process data
 HISTORY OF COMPUTERS
 First Generation: Vacuum Tubes
 ENIAC: The ENIAC (Electronic Numerical Integrator And
Computer), designed and constructed at the University of
Pennsylvania, was the world’s first general-purpose
electronic digital computer.
 The project was a response to U.S needs during World War II.
 THE VON NEUMANN MACHINE :The task of
entering and altering programs for the ENIAC was
extremely tedious.
 a computer could get its instructions by reading them from
memory This idea is known as the stored-program
concept. The first publication of the idea was in a 1945
proposal by von Neumann for a new computer, the
EDVAC (Electronic Discrete Variable Computer)
 In 1946, von Neumann and his colleagues began the
design of a new stored-program computer, referred to as
the IAS computer,
 The IAS machine was the first electronic computer to be
built at the Institute for Advanced Study in Princeton,
New Jersey.
 A main memory, which stores both data and instruction
 An arithmetic and logic unit (ALU) capable of operating
on binary data
 A control unit, which interprets the instructions in
memory and causes them to be executed
 Input and output (I/O) equipment operated by the control
unit
 Generations of Computers
 Generation in computer terminology is a change in
technology a computer is/was being used
 generation includes both hardware and software, which
together make up an entire computer system.
 There are five computer generations known till date
 First Generation
 The period of first generation: 1946-1959. Vacuum tube
based.
 Some computers of this generation were: • ENIAC •
EDVAC • UNIVAC
 Second Generation The period of second generation: 1959-
1965. Transistor based.
 In this generation, assembly language and high-level
programming languages like FORTRAN, COBOL were used.
 Some computers of this generation were: • IBM 1620 • IBM
7094 • CDC 1604 • CDC 3600
 Third Generation The period of third generation: 1965-1971.
Integrated Circuit based.
 High-level languages (FORTRAN-II TO IV, COBOL, PASCAL
PL/1, BASIC, ALGOL-68 etc.) were used during this generation.
 Some computers of this generation were: • IBM-360 series •
Honeywell-6000 series • PDP (Personal Data Processor)
 Fourth Generation The period of fourth generation: 1971-1980. VLSI
microprocessor based
 All the high-level languages like C, C++, DBASE etc., were used in this
generation.
 Some computers of this generation were: • DEC 10 • STAR 1000 • PDP
11 • CRAY-1(Super Computer) • CRAY-X-MP(Super Computer)
 Fifth Generation The period of fifth generation: 1980-onwards. ULSI
microprocessor based
 This generation is based on parallel processing hardware and AI
(Artificial Intelligence) software.
 All the high-level languages like C and C++, Java, .Net etc., are used in
this generation.
 Some computer types of this generation are: • Desktop • Laptop •
Notebook • Ultrabook • Chromebook
 The different types of computers are
 1. Personal computers: - This is the most common type
found in homes, schools, Business offices etc., It is the most
common type of desk top computers with processing and
storage units along with various input and output devices.
 2. Note book computers: - These are compact and portable
versions of PC
 3. Work stations: - These have high resolution input/output
(I/O) graphics capability, but with same dimensions as that
of desktop computer. These are used in engineering
applications of interactive design work.
 4. Enterprise systems: - These are used for business data
processing in medium to large corporations that require
much more computing power and storage capacity than
work stations. Internet associated with servers have
become a dominant worldwide source of all types of
information.
 5. Super computers: -These are used for large scale
numerical calculations required in the applications like
weather forecasting etc.,
Digital Computer
 Digital computers use the binary number system, which
has two digits: 0 and 1. A binary digit is called a bit.
Information is represented in digital computers in groups
of bits.
 All the content that is written in English will be converted
to binary language and thus computers and humans
communicate with each other.
 Some of the basic examples of digital devices are Personal
computers, Desktops, Laptops, Smartphones, and
Mobiles.
Review of Data Representation
 Data refers to the symbols that represent people, events,
things, and ideas. Data can be a name, a number, the
colors in a photograph, or the notes in a musical
composition
 Data Representation refers to the form in which data is
stored, processed, and transmitted.
 Devices such as smartphones, iPods, and computers store
data in digital formats that can be handled by electronic
circuitry
 Digitization is the process of converting information, such as
text, numbers, photo, or music, into digital data that can be
manipulated by electronic devices.
 The 0s and 1s used to represent digital data are referred to as
binary digits — from this term we get the word bit that stands
for binary digit. • A bit is a 0 or 1 used in the digital
representation of data
 Numeric data consists of numbers that can be used in
arithmetic operations.
 Digital devices represent numeric data using the binary
number system, also called base 2.
 The binary number system only has two digits: 0 and 1
 Digital devices employ several types of codes to represent
character data, including ASCII, Unicode, and their variants
 ASCII (American Standard Code for Information Interchange,
pronounced “ASK ee”) requires seven bits for each character.
• The ASCII code for an uppercase A is 1000001
 Extended ASCII is a superset of ASCII that uses eight bits for
each character.
 For example, Extended ASCII represents the uppercase letter
A as 01000001.
 Using eight bits instead of seven bits allows Extended ASCII
to provide codes for 256 characters
 Unicode (pronounced “YOU ni code”) uses sixteen bits
and provides codes or 65,000 characters. • This is a bonus
for representing the alphabets of multiple languages
 UTF-8 is a variable-length coding scheme that uses seven
bits for common ASCII characters but uses sixteen-bit
Unicode as necessary
 Each octal digit corresponds to three binary digits
 Each hexadecimal digit corresponds to four binary digits
 Rather than specifying numbers in binary form, refer to them in octal
or hexadecimal and reduce the number of digits by 1/3 or ¼,
respectively

 Complements are used in digital computers for simplifying

subtraction and logical manipulation
 Two types of complements for each base r system: r’s complement
and (r – 1)’s complement
 Fixed-Point Representation −
 This representation has fixed number of bits for integer part
and for fractional part. 
 Example −Assume number is using 32-bit format which
reserve 1 bit for the sign, 15 bits for the integer part and 16 bits
for the fractional part.
 Then, -43.625 is represented as following:

 Where, 0 is used to represent + and 1 is used to represent -

000000000101011 is 15 bit binary value for decimal 43 and
1010000000000000 is 16 bit binary value for fractional 0.625.
 Floating-Point Representation −
 This representation does not reserve a specific number of bits for the
integer part or the fractional part. Instead it reserves a certain number of
bits for the number (called the mantissa or significand) and a certain
number of bits to say where within that number the decimal place sits
(called the exponent).
 The floating number representation of a number has two part: the first part
represents a signed fixed point number called mantissa. The second part of
designates the position of the decimal (or binary) point and is called the
exponent.
 Only the mantissa m and the exponent e are physically represented in the
register (including their sign). A floating-point binary number is
represented in a similar manner except that is uses base 2 for the exponent.
 Example −+ 6132.789 is represented in floating-point with a
fraction and an exponent as follows:

 Fraction Exponent
+0.6132789 +04

A floating-point binary number is represented in a similar manner except

that it uses base 2 for the exponent. For example, the binary number + 1001
. 1 1 i s represented with a n 8-bit fraction and 6-bit exponent a s follows:

Fraction Exponent
00100111 000100
 Other Binary Codes
Gray Code
 Error Detection Codes
Whenever a message is transmitted, it may get scrambled by noise
or data may get corrupted. To avoid this, we use error-detecting
codes which are additional data added to a given digital message
to help us detect if an error occurred during transmission of the
message. A simple example of error-detecting code is parity
check.
 How to Detect and Correct Errors?
 To detect and correct the errors, additional bits are added to the
data bits at the time of transmission.
 The additional bits are called parity bits. They allow detection or
correction of the errors.
 The data bits along with the parity bits form a code word.
 Parity Checking of Error Detection
 It is the simplest technique for detecting and correcting
errors. The MSB of an 8-bits word is used as the parity bit
and the remaining 7 bits are used as data or message bits.
The parity of 8-bits transmitted word can be either even
parity or odd parity.
 Even parity -- Even parity means the number of 1's in the
given word including the parity bit should be even
(2,4,6,....).
 Odd parity -- Odd parity means the number of 1's in the
given word including the parity bit should be odd (1,3,5,....).
 The parity bit can be set to 0 and 1 depending on the type of
the parity required.
 For even parity, this bit is set to 1 or 0 such that the no. of "1
bits" in the entire word is even. Shown in fig. (a).
 For odd parity, this bit is set to 1 or 0 such that the no. of "1
bits" in the entire word is odd. Shown in fig. (b).
 How Does Error Detection Take Place?
 Parity checking at the receiver can detect the presence of
an error if the parity of the receiver signal is different from
the expected parity. That means, if it is known that the
parity of the transmitted signal is always going to be
"even" and if the received signal has an odd parity, then
the receiver can conclude that the received signal is not
correct. If an error is detected, then the receiver will
ignore the received byte and request for retransmission of
the same byte to the transmitter.
Instruction Codes
 A program is a set of instructions that specify the operations
operands, and the sequence by which processing has to occur.
 Instruction codes together with data are stored in memory.
The computer reads each instruction from memory and places
it in a control register.
 The control then interprets the binary code of the instruction
and proceeds to execute it by issuing a sequence of
microoperations.
 Every computer has its own unique instruction set..
 An instruction code is a group of bits that instruct the
computer to perform a specific operation.
 It is usually divided into parts.The most basic part of an
instruction code is its operation part. The operation code of
an instruction is a group of bits that define such operations
as add, subtract, multiply, shift, and complement.
 The number of bits required for the operation code of an
instruction depends on the total number of operations
available in the computer.
 The operation code must consist of at least n bits for a
given 2n (or less) distinct operations.
 For EX: a computer with 64 distinct operations, one of
them being an ADD operation. The operation code
consists of six bits, with a bit configuration 110010
assigned to the ADD operation .
 When this operation code is decoded in the control unit,
the computer issues control signals to read an operand
from memory and add the operand to a processor register .
 An instruction code must therefore specify not only
the operation but also the registers or the memory words where
the operands are to be found. as well as the register or memory
word where the result is to be stored.
 Stored Program Organization
The simplest way to organize a computer is to have one
processor register and an instruction code format with two parts.
 The first part specifies the operation to be performed and the
second specifies an address.
 The memory address tells the control where to find an operand in
memory. This operand is read from memory and used as the data
to be operated on together with the data stored in the processor
register
 For EX
 a memory unit with 4096 words we need 12 bits to
specify an address since 212 = 4096.
 If we store each instruction code in one 16-bit memory
word, we have available four bits for the operation code
(abbreviated opcode) and 12 bits to specify the address of
an operand.
 The control reads a16-bit instruction from the program
portion of memory.
 Computers that have a single-processor register usually assign to it the name
accumulator and label it AC. The operation is performed with the memory operand and
the content of AC.

 Indirect Address
 It is sometimes convenient to use the address bits of an instruction code not as an
address but as the actual operand.
 When the second part of an instruction code specifies an operand, the instruction is said
to have an immediate operand.
 When the second part specifies the address of an operand, the
instruction is said to have a direct address.
 a third possibility called indirect address, where the bits in the second part of the
instruction designate an address of a memory word in which the address of the operand
is found.
 One bit of the instruction code can be used to distinguish between a direct and an
indirect address.
 It consists of a 3-bit operation code, a 12-bit address, and an indirect address
mode bit designated by I. The mode bit is 0 for a direct address and 1 for an
indirect address.
 A direct address instruction . It is placed in address 22 in memory. The I bit is 0,
so
the instruction is recognized as a direct address instruction.
 The opcode specifies an ADD instruction, and the address part is the binary
equivalent of 457. The control finds the operand in memory at address 457 and
adds it to the content of AC.
 The instruction in address 35 has a mode bit I = 1. Therefore, it is recognized as
an indirect address instruction. The address part is the binary equivalent of 300.
The control goes to address 300 to find the address of the operand. The address
of the operand in this case is 1350.
 The operand found in address 1350 is then added to the content of AC. The
indirect address instruction needs two references to memory to fetch an operand.
 The first reference is needed to read the address of the
operand the second is for the operand itself.
 We define the effective address to be the address of the
operand in a computation-type instruction or the target
address in a branch-type instruction
 Thus the effective address in the instruction is 457 and in
the instruction is 1350.
Computer Instructions
 The basic computer has three instruction code formats, Each format has 16
bits A memory-reference instruction uses 12 bits to specify an address and
one bit to specify the addressing mode I. I is equal to 0 for direct address
and to 1 for indirect address
 The register reference instructions are recognized by the operation code 11l
with a 0 in the leftmost bit (bit 15) of the instruction.
 A register-reference instruction specifies an operation on or a test of the AC
register. An operand from memory is not needed; therefore, the other 12
bits are used to specify the operation or test to be executed.
 Similarly, an input-output instruction does not need a reference to memory
and is recognized by the operation code I l l with a 1 in the leftmost bit of
the instruction. The remaining 12 bits are used to specify the type of input-
output operation or test performed.
 The type of instruction is recognized by the computer control
from the four bits in positions 12 through 15 of the instruction.
 If the three opcode bits in positions 12 though 14 are not equal
to 1l l , the instruction is a memory-reference type and the bit in
position 15 is taken as the addressing mode I.
 If the 3-bit opcode is equal to 1ll, control then inspects the bit in
position 15. If this bit is 0, the instruction is a register-reference
type. If the bit i s 1, the instruction is an input output type.
 Note that the bit in position 15 of the instruction code is
designated by the symbol I but is not used as a mode bit when
the operation code is equal to 111.
 A memory-reference instruction has an address part of 12
bits. The address part is denoted by three
x's and stand for the three hexadecimal digits
corresponding to the 12-bit address.
 The last bit of the instruction is designated by the symbol I.
When I = 0, the last four bits of an instruction have a
hexadecimal digit equivalent from 0 to 6 since
the last bit is 0.
 When I = I, the hexadecimal digit equivalent of the last
four bits of the instruction ranges from 8 to E since the last
bit is I.
 Register-reference instructions use 16 bits to specify an
operation. The leftmost four bits are always 0111, which is
equivalent to hexadecimal 7.
 The other three hexadecimal digits give the binary
equivalent of the remaining 12 bits.
 The input-output instructions also use all 16 bits to specify
an operation. The last four bits are always 1111,
equivalent to hexadecimal F.
 Instruction Set Completeness
The set of instructions are said to be complete if the
computer includes a sufficient number of instructions in
each of the following categories:
1. Arithmetic, logical, and shift instructions
2. Instructions for moving information to and from
memory and processor registers
3. Program control instructions together with instructions
that check status conditions
4. Input and output Instructions
Instruction Cycle

In the basic computer each instruction cycle consists of the
following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction
has an indirect address.
4. Execute the instruction.
 Upon the completion of step 4, the control goes back to step 1
to fetch, decode, and execute the next instruction. This process
continues indefinitely unless a HALT instruction is
encountered.
 Fetch
  & Decode
 PC is loaded with the address of the first instruction in the program.
 The micro-operations for fetch and decode phases are as follows:

 Determine the type of instruction

• During time , the control unit determines the type of instruction i.e. Memory
reference, Register reference or Input-Output instruction.
• If then instruction must be register reference or input-output else memory
reference instruction
Instruction Formats

 The most common fields found in instruction formats are:

1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor
register.
3. A mode field that specifies the way the operand or the effective address
is determined

 A register address is a binary number of k bits that defines one of ‘2 k'

registers in the CPU.
 Thus a CPU with 16 processor registers R0 through R15 will have a
register address field of four bits. The binary number 0101, for example,
will designate register R5.
 Computers may have instructions of several different lengths
containing varying number of addresses
Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization
An example of an accumulator-type
The instruction format in this type of computer uses one address
field. For example, the instruction that specifies an arithmetic
addition is defined by an assembly language instruction as
ADD X
where X is the address of the operand. The ADD instruction in this
case results in the operation AC AC + M [X].
 An example of a general register type of organization
The instruction format in this type of computer needs three register address
fields. Thus the instruction for an arithmetic addition may be written in an
assembly language as
ADD R1 , R2 , R3 to denote the operation R1 R2 + R 3 . The number of
address fields in the instruction can be reduced from three to two if the
destination register is the same as one of the source registers.
 Thus the instruction ADD R1 , R2 would denote the operation R1  R1 +
R2. Only register addresses for R1 and
R2 need be specified in this instruction.
 Computers with multiple processor registers use the move instruction with a
mnemonic MOV to symbolize a transfer instruction.
 Thus the instruction MOV R1 , R 2 denotes the transfer R1  R2 (or R2
R1, depending o n the particular computer). Thus transfer-type instructions
need two address fields to specify the source and the destination.
 The stack-organized CPU
Computers with stack organization would have PUSH and POP instructions
which require an address field.
 Thus the instruction

PUSH X will push the word at address X to the top of thestack. The stack
pointer is updated automatically.
 Operation-type instructions do not need an address field in stack-organized
computers. This is because the operation is performed on the two items that
are on top of the stack.
 The instruction ADD in a stack computer consists of an operation code only
with no address field.
 This operation has the effect of popping the two top numbers from the stack,
adding the numbers, and pushing the sum into the stack.
 There is no need to specify operands with an address field since all operands
are implied to be inthe stack.
 To illustrate the influence of the number of addresses on
computer programs, we will evaluate the arithmetic statement
X = (A + B) • (C + D) using zero, one, two, or three address
instructions.
 We will use the symbols
ADD, SUB, MUL, and DIV for the four arithmetic operations;
MOV for the transfer-type operation; and LOAD and STORE
for transfers to and from memory and AC register.
 We will assume that the operands are in memory addresses A,
B, C, and D, and the result must be stored in memory
at address X.
 Three-Address Instructions
Computers with three-address instruction formats can use each address
field to specify either a processor register or a memory operand. The
program in assembly language that evaluates
 X = (A + B) • (C + D)

 ADD R1 , A , B R1  M [A] + M[B]

ADD R2 , C , D R2  M[C] + M[D]

MOL X , R1 , R2 M[X]  R1 • R 2

It is assumed that the computer has two processor registers, R1 and R2. The
symbol M [A] denotes the operand at memory address symbolized by A
 Two-Address Instructions
Two-address instructions are the most common in commercial
computers. Here again each address field can specify either a
processor register or a memory word.
 The program to evaluate X = (A + B) • (C + D)

 MO V R1 , A R1  M [ A ]
ADD R1 , B R1  R1 + M [ B ]
MO V R2 , C R2  M [ C ]
ADD R2 , D R2  R2 + M [ D ]
MUL R1 , R2 R1  R1 • R 2
MOV X , R1 M[ X ]R1
 The MOV instruction moves or transfers the operands to and from
memory and processor registers.
 One-Address Instructions
One-address instructions use an implied accumulator (AC) register for all data manipulation.
 For multiplication and division there is a need for a second
register. However, here we will neglect the second register and assume that
the AC contains the result of all operations.
 The program to evaluate X = (A + B) • (C + D) is
LOAD A A C  M[AJ
ADD B A C AC + M[B]
STORE T M[T] AC
LOAD C AC M [ C ]
ADD D AC AC+M[ D ]
MUL T AC AC• M[T]
STORE X M [ X ] A C

All operations are done between the AC register and a memory operand.
T is the address of a temporary memory location required for storing the
intermediate result.
 Zero-Address Instructions
A stack-organized computer does not use an address field for the
instructions ADD and MUL. The PUSH and POP instructions,
however, need an address field to specify the operand that
communicates with the stack.
 The following program shows how X = (A + B) • (C + D) will be
written for a stack organized computer. (TOS stands for top of
stack.)
 To evaluate arithmetic expressions in a stack computer, it
is necessary to convert the expression into reverse Polish
notation. The name "zero-address“ is given to this type of
computer because of the absence of an address field in
the computational instructions
 RISC Instruction
 The instruction set of a typical RISC processor is restricted to
the use of load and store instructions when communicating
between memory and CPU.
 All other instructions are executed within the registers of the
CPU without referring to memory.
 A program for a RISC type CPU consists of LOAD and
STORE instructions that have one memory and one register
address, and computational-type instructions that have three
addresses with all three specifying processor registers.
 The following is a program to evaluate X = (A + B) * (C + D)
Addressing Modes
 The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the operand
is actually referenced.
 Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
1. To give programming versatility to the user by providing such
facilities as pointers to memory, counters for loop control, indexing
of data, and program relocation.
2. To reduce the number of bits in the addressing field of the
instruction.
 There are basic 10 addressing modes supported by the computer.
1. Implied Mode
2. Immediate Mode
3. Register Mode
4. Register Indirect Mode
5. Auto increment or Auto decrement Mode
6. Direct Address Mode
7. Indirect Address Mode
8. Relative Address Mode
9. Indexed Addressing Mode
10. Base Register Addressing Mode
Implied Mode
 Operands are specified implicitly in the definition of the
instruction.
 For example, the instruction “complement accumulator
(CMA)” is an implied-mode instruction because the
operand in the accumulator register is implied in the
definition of the instruction.
 In fact, all register reference instructions that use an
accumulator and zero address instructions are implied
mode instructions
Immediate Mode
 Operand is specified in the instruction itself.
 In other words, an immediate-mode instruction has an
operand field rather than an address field.
 The operand field contains the actual operand to be used
in conjunction with the operation specified in the
instruction.
 Immediate mode of instructions is useful for initializing
register to constant value.
 E.g. MOV R1, 05H
instruction copies immediate number 05H to R1 register.
Register Mode
 Operands are in registers that reside within the CPU.
 The particular register is selected from a register field in
the instruction.
 E.g. MOV AX, BX
move value from BX to AX register
Register Indirect Mode
 In this mode the instruction specifies a register in the CPU
whose contents give the address of the operand in memory.
 Before using a register indirect mode instruction, the
programmer must ensure that the memory address of the
operand is placed in the processor register with a previous
instruction.
 The advantage of this mode is that address field of the
instruction uses fewer bits to select a register than would
have been required to specify a memory address directly.
 E.g. MOV [R1], R2
value of R2 is moved to the memory location specified in R1
Autoincrement or Autodecrement Mode
 This is similar to the register indirect mode expect that the
register is incremented or decremented after (or before) its
value is used to access memory.
 When the address stored in the register refers to a table of
data in memory, it is necessary to increment or decrement
the register after every access to the table. This can be
achieved by using the increment or decrement instruction.
Direct Address Mode
 In this mode the effective address is equal to the address
part of the instruction.
 The operand resides in memory and its address is given
directly by the address field of the instruction.
 E.g. ADD 457
Indirect Address Mode
 In this mode the address field of the instruction gives the
address where the effective address is stored in memory.
 Control fetches the instruction from memory and uses its
address part to access memory again to read the effective
address.
 The effective address in this mode is obtained from the
following computational:
Effective address = address part of instruction + content of
CPU register
Relative Address Mode
 In this mode the content of the program counter is added
to the address part of the instruction in order to obtain the
effective address.
 The address part of the instruction is usually a signed
number which can be either positive or negative.
Effective address = address part of instruction + content of
PC
Indexed Addressing Mode
 In this mode the content of an index register is added to
the address part of the instruction to obtain the effective
address.
 The indexed register is a special CPU register that contain
an index value.
 The address field of the instruction defines the beginning
address of a data array in memory.
 Each operand in the array is stored in memory relative to
the begging address.
Effective address = address part of instruction + content of
index register
Base Register Addressing Mode
 In this mode the content of a base register is added to the
address part of the instruction to obtain the effective
address.
 A base register is assumed to hold a base address and the
address field of the instruction gives a displacement
relative to this base address.
 The base register addressing mode is used in computers to
facilitate the relocation of programs in memory.
Effective address = address part of instruction + content of
base register
 Numerical Example
The two-word instruction at address 200 and 201 is a "load
to AC" instruction with an address field equal to 500.
 The first word of the instruction specifies the operation
code and mode, and the second word specifies the address
part.
 PC has the value 200 for fetching this instruction. The
content of processor register R 1 is 400, and the content of
an index register XR is 100. AC receives the operand after
the instruction is executed.
 In the direct address mode the effective address is the
address part of the instruction 500 and the operand to be
loaded into AC is 800. In the immediate mode the second
word of the instruction is taken as the operand rather than
an address, so 500 is loaded into AC
 In the indirect mode the effective address
is stored in memory at address 500. Therefore, the
effective address is 800 and
the operand is 300.
 In the relative mode the effective address is 500 + 202 =
702 and the operand is 325. (Note that the value in PC after the fetch
phase and during the execute phase is 202.) In the index mode the
effective address is XR + 500 = 100 + 500 = 600 and the operand is 900.
 In the register mode the operand is in R 1 and 400 is loaded into AC .
(There is no effective address in this case.)
 In the register indirect mode the effective address is 400, equal to
the content of R 1 and the operand loaded into AC is 700.
 The autoincrement mode is the same as the register indirect mode except
that R 1 is incremented to 401 after the execution of the instruction.
 The autodecrement mode decrements R1 to 399 prior to the execution of
the instruction. The operand loaded into AC is now 450.
Reduced Instruction Set Computer (RISC)
 Characteristics of RISC are as follows:
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instructions
 All operations done within the registers of the CPU
 Fixed-length, easily decoded instruction format
 Single-cycle instruction execution
 Hardwired rather than microprogrammed control
 A relatively large number of registers in the processor unit
 Use of overlapped register windows to speed-up procedure call and return
 Efficient instruction pipeline
 Compiler support for efficient translation of high-level language programs
into machine language programs
Complex Instruction Set Computer (CISC)
 Characteristics of CISC are as follows:
 A larger number of instructions – typically from 100 to 250
instructions
 Some instructions that perform specialized tasks and are used
infrequently
 A large variety of addressing modes – typically from 5 to 20
different modes
 Variable-length instruction formats
 Instructions that manipulate operands in memory
 Overlapped Register Window
 A characteristic of some RISC processors is their use of
overlapped register windows to provide the passing of
parameters and avoid the need for saving and restoring
register values.
 Each procedure call results in the allocation of a new
window consisting of a set of registers from the register
file for use by the new procedure.
 Windows for adjacent procedures have overlapping
registers that are shared to provide the passing of
parameters and results.
 number of global registers = G
number of local registers in each window = L
number of registers common to two windows = C
number of windows = W

 Overlapped Register Window

 Suppose that procedure A calls procedure B.
 Registers R26 through R31 are common to both procedures, and
therefore procedure A stores the parameters for procedure B in these
registers.
 Procedure B uses local registers R32 through R41 for local variable
storage.
 If procedure B calls procedure C, it will pass the parameters through
registers R42 through R47.
 When procedure B is ready to return at the end of its computation, the
program stores results of the computation in registers R26 through R31
and transfers back to the register window of procedure A.
 Note that registers R10 through R15 are common to procedures A and D
because the four windows have a circular organization with A being
adjacent to D.