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VLSI Arithmetic Lect 3
VLSI Arithmetic Lect 3
VLSI Arithmetic Lect 3
http://www.ece.ucdavis.edu/acsel
Introduction
• Digital Computer Arithmetic belongs to
Computer Architecture, however, it is also an
aspect of logic design.
• The objective of Computer Arithmetic is to
develop appropriate algorithms that are
utilizing available hardware in the most
efficient way.
• Ultimately, speed, power and chip area are
the most often used measures, making a
strong link between the algorithms and
technology of implementation.
Oklobdzija 2004 Computer Arithmetic 2
Basic Operations
• Addition
• Multiplication
• Multiply-Add
• Division
• Evaluation of Functions
• Multi-Media
Carry-Propagate: pi ai bi
and Carry-Generate gi
g i a i bi
c out
c in
One-bit adder could be
implemented as shown
si
Oklobdzija 2004 Computer Arithmetic 7
High-Speed Addition
ci 1 g i pi ci
a i b i
g i ai bi pi ai bi
0
c out
s 1 c in
S0 S1 S2 S3
A B A B
Ci FA Co Ci FA Co
S S
S A B C i = S A B Ci
C o A B C i = Co A B Ci
From Rabaey
Oklobdzija 2004 Computer Arithmetic 11
Minimize Critical Path by Reducing Inverting
Stages
A1 B1 A3 B3
A0 B0 A2 B2
S0 S2
S1 S3
Critical Path
c i+ 1 ci
c out c in
Oklobdzija, ISCAS’88
s i+ 2 s i+ 1 si
V dd
V dd
V dd
V dd
V dd
V dd
V dd
V dd
Generate
device
Carry out Carry in
+ + + + + + + + Propagate
devic e
Predis charge
& kill devic e
P0 P1 P2 P3 P4
Ci,0
G0 G1 G2 G3 G4
X O R /X N O R M U L T IP L E X E R B U FFER
A N D /N A N D
V C C
A
A C C
B V C C
C
B O
V C C
A C O
A
B M U L T IP L E X E R B U FFER
B
O R /N O R
P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA
Multiplexer
Co,3
Bypass
Idea: If (P0 and P1 and P2 and P3 = 1)
From Rabaey
then C o3 = C 0, else “kill” or “generate”.
a b (r-1 )k a a b a0 b
a a
N - 1 b N - 1 N - k - 1b N - k - 1 (r-1 )k (r-1 )kb (r-1 )k a 2 k -1
b 2 k -1
ak bk k -1 k -1 0
S S S S S S S S
N -1 N -k -1 (r-1 )k -1 (r-2 )k 2 k -1 k k -1 0
P r-1
P r-2 P 1 P 0
...
AND AND AND AN D
c r it ic a l p a t h , d e la y = 2 ( k - 1 ) + ( N / 2 - 2 )
tp
ripple adder
bypass adder
N
t d 2 k 1 t RCA 2 t SKIP
2k
4..8
N
Oklobdzija 2004 Computer Arithmetic 21
Variable Block Adder
(Oklobdzija, Barnes: IBM 1985)
a b ajb a b a0 b
N -1 N -1 j i i 0
..
.. ... ... ... ..
.
C out
G G G G 2 G 1 G C in
m m -1 m -2 0
S S S S 0
N -1 j i
P m P m -1 P m -2 P 2 P 1
P 0
G m
G m -1
G m -2
... G 2
G 1
G 0
s k ip in g
...
C ou
C in
t
C a r r y s ig n a l p a th
r ip p lin g
6
5 5
4 4
1 3 =9 3 1
Any-point-to-any-point delay = 9
as compared to 12 for CSKA
P0 P1 P2 P3 BP
Ci,0 Co,3
G0 G1 G2 G3
BP
Delay model:
t d c1 c2 N c3
Delay 16
14 VBA
12
CLA
10
8
VBA- Multi-Level
6
0
4 11 18 25 32 39 46 53 60
Size N