Analog to Digital Converters

Nyquist-Rate ADCs
 Flash ADCs
 Sub-Ranging ADCs
 Folding ADCs
 Pipelined ADCs
 Successive Approximation (Algorithmic) ADCs
 Integrating (serial) ADCs

Oversampling ADCs
 Delta-Sigma based ADCs

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 Conversion Principles

Principle Resolution Speed Cost

Serial High Low Low

Conversion >12 Bit <1kHz

Successive Medium Medium Medium

Approximation 8-14 Bit <10MHz

Parallel Low High High

Conversion 6-10 Bit <100MHz

Delta High Low-Medium Low

Sigma >12 Bit <1MHz (analog only)

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 ADC Architectures

 Flash ADCs: High speed, but large area and high power dissipation.
Suitable for low-medium resolution (6-10 bit).
 Sub-Ranging ADCs: Require exponentially fewer comparators than
Flash ADCs. Hence, they consume less silicon area and less power.
 Pipelined ADCs: Medium-high resolution with good speed. The trade-
offs are latency and power.
 Successive Approximation ADCs: Moderate speed with medium-
high resolution (8-14 bit). Compact implementation.
 Integrating ADCs or Ramp ADCs: Low speed but high resolution.
Simple circuitry.
 Delta-Sigma based ADCs: Moderate bandwidth due to oversampling,
but very high resolution thanks to oversampling and noise shaping.

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 Performance Limitations 1
System Definitions
 n-Bit ADC
 Sinusoidal Input
 Swing: ±1[V]
 fmax= ½ fconv

Thermal Noise Limitation Clock Jitter (Aperture) Limitation

Normalized Noise Powers: fin=½fconv

1 1
PNTH  2 kTReq f conv PQuant  2 2 n PN Jitter  ( f conv t Jitter )2
3 2

Limiting Condition:
PQuant  PNTH PQuant  PN Jitter
Maximum Resolution:

1  1  1  1 
n log   n log  
  
2 log 2  6 kTR f
eq conv  log 2  1.5  f conv t Jitter 

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 Performance Limitations 2

Displays

Seismology

Audio
Sonar
Wireless
Ultra Communications
Sound

Video

 Selection of ADC Architecture is driven by Application

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 Parallel or Flash ADCs
Conceptual Circuit

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 Sub-Ranging ADCs

Half-Flash or Two-Step ADC

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 Folding ADCs

Principle Configuration

…
2n1 Sub-Ranges

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 Folding Processor
Example: 2-Bit Folding Circuit

(2n-1+1)Io for n-Bit

2Io

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 Successive Approx. ADCs

Concept Implementation

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 DAC Realization 1
(Voltage Mode)

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 DAC Realization 2
Spread Reduction through R-2R Ladder

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 DAC Realization 3
Charge-Redistribution Circuit

valid only during 2

Pros Cons
 Insensitive w.r.t. Op-amp Gain  Requires non-overlapping Clock
 Offset (1/f Noise) compensated  High Element Spread  Area
 Output requires S&H

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 DAC Realization 4
Spread Reduction through capacitive Voltage Division

Example: 8-Bit ADC

valid only during 2

1 3 7

Vout  Vref   bi 2( i 4 )   bi 2( i 8) 
16 i 0 i 4 

Spread=2n/2

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 DAC Realization 5
Charge-Redistribution Circuit with Unity-Gain Amplifier
Example: 8-Bit ADC
Amplifier Input Cap.
16/15C

1 3 7
 Spread=½2n/2
Vout  Vref   bi 2( i 4)   bi 2(i 8) 
16 i 0 i 4  Cp  Gain Error: єG=-Cp/16C

Pros Cons
 Voltage divider reduces spread  Parasitic cap causes gain error
 Buffer  low output impedance  High Op-amp common mode input required
 No clock required  No amplifier offset compensation

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 DAC8 with Unity-Gain Amplifier

Sub-range Output (4 LSBs) Amplifier Output

0 0.5u 1u 1.5u 2u 2.5u 3u 3.5u 4u 4.5u 5u 5.5u 6u 6.5u 0 0.5u 1u 1.5u 2u 2.5u 3u 3.5u 4u 4.5u 5u 5.5u 6u 6.5u

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 DAC Realization 6
Current Mode Implementation

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 Current Cell & Floor Plan
Symmetrical Current Cell Placement
Array of 256 Cells Iout Current summing Rail
Unit Current Cell R

Switching
Devices

Cascode
Current
Source

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 DAC Implementation
Layout of 10-Bit Current-Mode DAC (0.5m CMOS)
Current summing Rails

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 Modified SA Algorithm 1

Idea: Replace DAC by an Accumulator

 Consecutively divide Ref by 2

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 Modified SA Algorithm 2

Idea: Maintain Comparator Reference (½ FS=Gnd)

 Double previous Accumulator Output

First cycle only

Accumulator

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 SC Implementation
SC Implementation of modified SA ADC

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 Timing Diagram

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 Offset Compensated Circuit
Offset Compensated SC Implementation

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 Building Blocks 1
Transconductance Amplifier

DC Gain 77 dB
Gain- 104 MHz @
bandwidth CL= 1.5 pF
Power 1.3 mW
Output 4 V p-p
Swing

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 Building Blocks 2
Latched CMOS Comparator

Power 0.5 mW
Resolution > 0.5 mV
Settling Time 3 ns

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 Layout of 8-Bit ADC

165 m (0.5 m CMOS)

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 Spice Simulation (Bsim3)
8-Bit ADC: fclk=10MHz  fconv=1.25MHz

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 Pipelined ADCs
Pipelined modified SA or Algorithmic ADC

Pros Cons
 Offset (1/f Noise) compensated  Matching errors  digital correction for n>8
 Minimum C-spread  Clock feed-through very critical
 One conversion every clock period  High amplifier slew rate required

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 Integrating or Serial ADCs

Dual Slope ADC Concept

Constant Ramp
Prop. to Input Ramp

Using 2N/k samples requires Ref = FS/k N represents digital

 reduced Integrator Constant equivalent of analog Input
(Element Spread)

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 SC Dual-Slope ADC
10-Bit Dual-Slope ADC

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 ADC Testing
Types of Tests
 Static Testing
 Dynamic Testing

Circuit
Input Output
Under Test

Clock

 In static testing, the input varies slowly to reveal the actual code
transitions.  Yields INL, DNL, Gain and Offset Error.

 Dynamic testing shows the response of the circuit to rapidly

changing signals. This reveals settling errors and other dynamic
effects such as inter-modulation products, clock-feed-trough, etc.

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 Performance Metrics 1
Static Errors

IDEAL ADC

Error Types
 Offset  INL
 Gain  Missing Codes
 DNL
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 Performance Metrics 2
Frequency Domain Characterization

PSignal
SNR  10 log10
PNoise

PSignal
SNDR  10 log10
Amplitude

PNoise  PHarm

SNDRmax [dB ] 3
 log10 ( )
ENOB  10 2
2 log10 2

Ideal n-Bit ADC:

fsig SNR = 6.02 x n + 1.76 [dB]

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 ADC Error Sources

Static Errors
 Element or Ratio Mismatches
 Finite Op-amp Gain
 Op-amp & Comparator Offsets
 Deviations of Reference

Dynamic Errors
 Finite (Amplifier) Bandwidth
 Op-amp & Comparator Slew Rate
 Clock Feed-through
 Noise (Resistors, Op-amps, switched Capacitors)
 Intermodulation Products (Signal and Clock)

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 Static Testing
Servo-loop Technique

 Comparator, integrator, and ADC under test are in negative feedback

loop to determine the analog signal level required for every digital code
transition.
 Integrator output represents equivalent analog value of digital output.
 Transition values are used to generate input/output characteristic of ADC,
which reveals static errors like Offset, Gain, DNL and INL.

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 Dynamic Testing
Test Set-up

Types of Dynamic Tests

 Histogram or Code-Density Test
 FFT Test
 Sine Fitting Test

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 Histogram or Code-Density Test

 DNL appears as deviation of

bin height from ideal value.
 Integral nonlinearity (INL) is
cumulative sum (integral) of
DNL.
 Offset is manifested by a
horizontal shift of curve.
 Gain error shows as
horizontal compression or
decompression of curve.

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 Histogram Test

Pros and Cons of Histogram Test

 Histogram test provides information on each code
transition.
 DNL errors may be concealed due to random noise in
circuit.
 Input frequency must be selected carefully to avoid
missing codes (fclk/fin must be non-integer ratio).
 Input Swing is critical (cover full range)
 Requires a large number of conversions (o 2 n x 1,000).

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 Simulated Histogram Test

8-Bit SA ADC with 0.5%

Ratio Error and 5mV/V
Comparator Offset

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 FFT Test

Pros and Cons of FFT Test

 Offers quantitative Information on output Noise, Signal-
to-Noise Ratio (SNR), Spurious Free Dynamic Range
(SFDR) and Harmonic Distortion (SNDR).
 FFT test requires fewer conversions than histogram
test.
 Complete characterization requires multiple tests with
various input frequencies.
 Does not reveal actual code conversions

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 Simulated FFT Test

8-Bit SA ADC with 0.5% Ratio Error and 5mV/V Comparator Offset

SNDR=49 dB
 ENOB=7.85
SFDR=60 dB

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