Design and Implementation of Parallel to Serial

Data Transmission using Aurora Protocol for

High Speed Serial Data Transmission on Virtex 5
FPGA.

Project Guide : M R VENKAT SAI

Kurakula Madhukar 221710402034
ECE –A2
 Contents
• Aim
• Proposed Work
• Explanation
• Implementation
• Results
• Future Scope
• References
Aim

• Establish high speed serial data transmission by employing the architectural

features of Virtex-5 FPGA and transmitting the assigned data through an
SFP. By using this, the high speed serial data is transmitted at the rate of
3.125 Gbps for aurora and 1 Gbps for integrated module of Ethernet and
Aurora.
Parallel and Serial Transmission
Example:
•Number of bits =9
•Time taken for each bit to transmit =1 sec.

•Then Why Serial Over Parallel?

About Fpga
8b/10b Aurora Protocol
• The Aurora 8B/10B protocol is a scalable, lightweight, link-layer protocol that can be used to move
data point-to-point across one or more high-speed serial lanes. The Aurora 8B/10B protocol is an open
standard and is available for implementation by anyone without restriction. (protocol generation
through source code).
Applications

• Aurora 8B/10B cores can be used in a wide variety of applications because of their low resource cost,
scalable throughput, and flexible data interface.
Examples of Aurora 8B/10B core applications include:
• Chip-to-chip links
• Board-to-board and backplane links
• Simplex connections (unidirectional)
• ASIC applications
 Multi Gigabit Transreceiver’s (MGT’s)

• Today’s high end FPGA’s include special type hard wired Gigabit Transceiver blocks . These High
Speed serial interfaces use one pair of differential signals to transmit data and another pair to receive
data.
• The reason for using differential pairs is that these signals are less susceptible to noise from an
external source , such as radio interference or another signal switching in close proximity to these
tracks.
• The main function of these MGT’s are to
convert the parallel data into serial data
and vice versa and this action is performed
by configuring the MGT’s using aurora core.

• The MGT’s are configured as either

transmitter or receiver to perform the data
transmission.
Implementation/Simulation

• The resources used for design and

implementation of the high speed data
transmission are as follows:
A. Software Resources:
1. Xilinx ISE
2. Xilinx core generator tool
B. Hardware Resources:
1. Virtex-5 ML507 board
2. SFP Transceivers
2. Fibre optic cable
3. Switch Mode Power Supply(SMPS)
4. JTAG cable
• Multi-gigabit transceivers are present in FPGA and we use two different MGT’s which
belongs to one GTX dual tile. These MGT’s are configured using aurora protocol for
developing the application of dual independent aurora channels for high speed serial data
transmission at the rate of
3.125 GB/s.
•  Select the aurora lane = 1, lane width = 4 bytes, line rate 3.125Gbps, dataflow mode =
duplex, interface = streaming, flow control = none.
• Select any one of the Tile for ex, GTX_DUAL_X0Y6_0. Next click on generate, the aurora
source code for X0Y6_0 was generated.
Simulation /Test Bench/ Chip Scope/ IBERT
RESULTS
IBERT / Chipscope Analyser
 Conclusion

• The 32-bit parallel data is transmitted serially at the rate of 3.125Gbps over
dual independent aurora links present on one GTX DUAL TILE through SFP
using multi gigabit transceivers and they are received by the multi-gigabit
transceivers of the same TILE using loop back SFP. Finally, both the
transmitted data and received data are verified by using logic analyzer
software.
 Future Scope

• The present experiment was implemented on dual independent aurora links on one GTX
DUAL TILE for serial data transmission at the rate of 3.125Gbps using aurora protocol. We
can achieve the 6.25Gbps speed also with some other vertex series boards which supports
6.25Gbps line rate using aurora protocol. The other protocol is Serial Rapid IO (SRIO) which
works on the principle of data packets switching, which is more efficient for error free
transmission and speeds can be increased to higher level.
 References

• Xilinx, Aurora 8b/10b protocol specification, available at

“http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b_protocol_spec_sp
002.pdf ”, SP002 (v2.2) April 19, 2010.
• Xilinx, LogiCORE ip aurora 8b/10 v6.2 user guide . 2010 Jul 23.
• “Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide” (v1.10), Xilinx, San Jose, CA.
• “Chip-scope pro integrated bit error ratio test (IBERT) for virtex-5 FPGA GTX” (v2.01a), DS774, Xilinx,
San Jose, CA, October, 2011.
Thank You