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Flip Flop
Flip Flop
Flip Flop
Edge-Triggered Flip-flops
S-R Flip-flop
D Flip-flop
J-K Flip-flop
T Flip-flop
Asynchronous Inputs
CS1104-11 Lecture 11: Sequential Logic: 2
Latches & Flip-flops
Introduction
A sequential circuit consists of a feedback path,
and employs some memory elements.
Combinational
outputs Memory outputs
Combinational Memory
logic elements
External inputs
CS1104-11 Introduction 3
Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time
CS1104-11 Introduction 4
Memory Elements
Memory element: a device which can remember
value indefinitely, or change value on command
from its inputs.
Memory Q
command element stored value
Characteristic table:
Command Q(t) Q(t+1)
(at time t) Q(t): current state
Set X 1
Q(t+1) or Q+: next state
Reset X 0
Memorise / 0 0
No Change 1 1
Memory Q
command element stored value
clock
Pulse-triggered
latches
ON = 1, OFF = 0
Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1; OFF = other
time)
negative edge-triggered (ON = from 1 to 0; OFF = other
time)
D
Q D Q
EN EN
Q' Q'
Clock signal
S Q D Q J Q
C C C
R Q' Q' K Q'
S Q D Q J Q
C C C
R Q' Q' K Q'
CS1104-11 SR Flip-flop 16
S-R Flip-flop
It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector) circuit
CS1104-11 SR Flip-flop 17
S-R Flip-flop
The pulse transition detector.
S
Q
Pulse
CLK transition
detector
Q'
R
CLK' CLK'
CLK CLK* CLK CLK*
CLK CLK
CLK' CLK'
CLK* CLK*
CS1104-11 D Flip-flop 19
J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulse-
steering NAND gates.
No invalid state.
Include a toggle state.
J=HIGH (and K=LOW) SET state
K=HIGH (and J=LOW) RESET state
both inputs LOW no change
both inputs HIGH toggle
Characteristic table.
T CLK Q(t+1) Comments Q T Q(t+1)
0 Q(t) No change 0 0 0
1 Q(t)' Toggle 0 1 1
1 0 1
1 1 0
Q(t+1) = T.Q' + T'.Q
CS1104-11 T Flip-flop 22
End of segment