Digital Electronics

(DE)

II Year - II Semester
JNTUK, Kakinada

UNIT-1 : Review of Number Systems & Codes

(Module-III)

By

Mr. B.ASHOK KUMAR

Associate Professor
Department of EEE,
Ramachandra College of Engineering, Eluru

Department of EEE, Ramachandra College of Engineering, Eluru

 Contents
1.Conversion from Normal SOP & POS forms to
Canonical forms

2. M-Notations

3. Universal Building Blocks

4. Error correction and Detection codes

Department of EEE, Ramachandra College of Engineering, Eluru

 Steps to convert normal SOP form to Standard SOP form

1. Find out the missing literal in each product term

2. “AND” each product term having missing literal by “OR”ing the literal
and its complement

3. Expand the expression using Distributive law

4. Reduce the expression

Ex: f(A,B,C) = AB + BC + AC

Department of EEE, Ramachandra College of Engineering, Eluru

 Steps to convert normal POS form to Standard POS form

1. Find out the missing literal in each sum term

2. “OR” each sum term having missing literal by “AND”ing the literal

and its complement

3. Expand the expression using Distributive law

4. Reduce the expression

Ex: f(A,B,C) = (A+B).(B+C).(A+C)

Department of EEE, Ramachandra College of Engineering, Eluru

 M-Notations

1. The product terms in SOP form are called “Min” terms and can be

expressed as Σm(product terms)

2. The sum terms in POS form are called “Max” terms and can be

expressed as πM(sum terms)

3. For M-Notations,

The minimum terms can be shown in compliment form for SOP form

Ex: 101 -------- A B’C

110 -------- ABC’

The max terms can be shown in compliment form for POS form

Ex: 101 -------- A’ + B + C’

110 -------- A’ + B’ + C

Department of EEE, Ramachandra College of Engineering, Eluru

 M-Notations

Ex: f(A,B,C) = A’B’C’ + ABC + ABC’ + A’BC’. Write the expression in

M-Notation form

Ex: f(A,B,C) = (A’+B’+C’) + (A+B+C) + (A+B+C’) + (A’+B+C’). Write the

expression in M-Notation form

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
The NAND and NOR gates are called Universal Gates since any logic function
can be implemented using NAND or NOR Gates

Implementations

Using NAND Gate Using NOR Gate

1. NOT Gate 1. NOT Gate

2. AND Gate 2. OR Gate
3. OR Gate 3. AND Gate
4. NOR Gate 4. NAND Gate
5. X-OR Gate 5. X-OR Gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
NOT Gate Implementation using NAND Gate

Actual Representation of NOT Gate and its Truth table

Using NAND gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
AND Gate Implementation using NAND Gate

Actual Representation of AND Gate and its Truth table

Using NAND gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
OR Gate Implementation using NAND Gate

Actual Representation of OR Gate and its Truth table

Using NAND gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
NOR Gate Implementation using NAND Gate

Actual Representation of NOR Gate and its Truth table

Using NAND gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
X-OR Gate Implementation using NAND Gate
Actual Representation of X-OR Gate and its Truth table

Using NAND gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
NOT Gate Implementation using NOR Gate
Actual Representation of NOT Gate and its Truth table

Using NOR gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
OR Gate Implementation using NOR Gate
Actual Representation of OR Gate and its Truth table

Using NOR gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
AND Gate Implementation using NOR Gate
Actual Representation of AND Gate and its Truth table

Using NOR gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
NAND Gate Implementation using NOR Gate
Actual Representation of NAND Gate and its Truth table

Using NOR gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Universal Building Blocks
X-OR Gate Implementation using NOR Gate
Actual Representation of X-OR Gate and its Truth table

Using NOR gate

Department of EEE, Ramachandra College of Engineering, Eluru

 Error Detection and Error Correction Codes
When the digital information in binary form is transmitted from one
circuit or system to another circuit or system, an error may occur.

To maintain the data integrity between transmitter and receiver, extra bit
or more than one bit are added in the data. These extra bits allow the
direction and some times correction of error in the data.

The data along with the extra bits/ bits forms the code. The Codes which
allow only error detection are called Detecting codes.

The codes which allow error detection and correction are called error
detecting and correcting codes.

The extra bits which are used to detect and correct the error are called
Parity Bits.

Two types of Parity ------1. Even parity 2. odd parity

Department of EEE, Ramachandra College of Engineering, Eluru

 Error Detection and Error Correction Codes

Hamming code

Hamming code not only provides the detection of a bit error, but
also identifies which bit is in error so that it can be corrected.

Thus Hamming code is called “Error Detecting and Correcting

Code”

Steps involved to Find out Hamming Code

1.Find no. of parity bits required

2. Identify Location of parity bits in the code

3. Assign the values to Parity Bits

Department of EEE, Ramachandra College of Engineering, Eluru

 Example Problem to find out Hamming code
Find Hamming code for the Given Information bits 1011 using Even parity

Step:1 Find No. of Parity Bits required

2P ≥ x + P + 1 Where, x = No. of Information bits given

P = No. of Parity bits required

We can find out No. of Parity bits required using Train and Error method

No. of Information bits given, x= 4

(i)Let P=2, then 22 ≥ 4 +2+1

4 ≥ 7 ------ The condition is not satisfied

(ii) Let P=3, then 23 ≥ 4 +3+1

8 ≥ 8 ------ The condition is satisfied

Therefore, No. of Parity bits required, P=3

Department of EEE, Ramachandra College of Engineering, Eluru

 Example Problem to find out Hamming code
Find Hamming code for the Given Information bits 1011 using Even parity

Step:2 Identify Location of Parity bits in the code

Parity bits can be placed in 1, 2, 4, 8, 16, 32 ……..positions

In the given data, no. of Information bits given, x = 4.

Therefore, Location of Parity bits is as follows

D7 D6 D5 P4 D3 P2 P1

Department of EEE, Ramachandra College of Engineering, Eluru

 Example Problem to find out Hamming code
Find Hamming code for the Given Information bits 1011 using Even parity

Step:3 Assign the values to Parity Bits

Assign the Values to Parity Bits

Bit Designation D7 D6 D5 P4 D3 P2 P1
Bit Location 7 6 5 4 3 2 1

Bit Location value 111 110 101 100 011 010 001

Given Information Bits 1 0 1 X 1 X X

Parity Bits ? ? ?
TABLE-1

Department of EEE, Ramachandra College of Engineering, Eluru

 Example Problem to find out Hamming code
To find P1: To find P1
Observe the Bit Location values where we can find ‘1’
in the First bit position from TABLE-1 in previous slide. P1 D3 D5 D7
We can observe that P1, D3, D5, D7 are having ‘1’ in the X 1 1 1
first bit position. Write down corresponding Information bit value
as shown in side table. ie P1 =X (We don’t Know), D3=1, D5 =1, D7=1

From the side table, No. of 1’s = 3. To get Even parity, P1 should be equal to 1

To find P2: To find P2

Observe the Bit Location values where we can find ‘1’
in the Second bit position from TABLE-1 in previous slide. P2 D3 D6 D7
We can observe that P1, D3, D5, D7 are having ‘1’ in the X 1 0 1
Second bit position. Write down corresponding Information bit value
as shown in side table. ie P2 =X (We don’t Know), D3=1, D6 =0, D7=1

From the side table, No. of 1’s = 2. To get Even parity, P2 should be equal to 0

Department of EEE, Ramachandra College of Engineering, Eluru

 To find P4:
Observe the Bit Location values where we can find ‘1’
in the Third bit position from TABLE-1 in previous slide. To find P4
We can observe that P4, D5, D6, D7 are having ‘1’ in the P4 D5 D6 D7
Third bit position. Write down corresponding Information
bit value as shown in side table. ie P4 =X (We don’t Know), X 1 0 1
D5=1, D6 =0, D7=1
From the above table, No. of 1’s = 2. To get Even parity, P4 should be equal to 1
Fill values of P1, P2, P4 in the down table, We will get final hamming code
Assign the Values to Parity Bits
Bit Designation D7 D6 D5 P4 D3 P2 P1
Bit Location 7 6 5 4 3 2 1
Bit Location value 111 110 101 100 011 010 001
Given Information Bits 1 0 1 X 1 X X
Parity Bits 1 0 0

The Hamming code of given 1011 is 1011100

Department of EEE, Ramachandra College of Engineering, Eluru

 Outcomes of the Topic

Students can be able to learn

1.Conversion normal SOP & POS forms to Standard SOP &

POS forms

2.Universal Building Blocks

3.Error detection & correction codes

Department of EEE, Ramachandra College of Engineering, Eluru

Department of EEE, Ramachandra College of Engineering, Eluru
Department of EEE, Ramachandra College of Engineering, Eluru