FIFO

MEMORY
USING
VERILOG

Department of Computer
Science and Engineering,
Amrita Vishwa Vidyapeetham
TEAM MEMBERS
 MARREDDI DHANUSH
 CHOWDAVARAPU DHANUNJAY
 MAAKAM VENKATA SRI GAURAV
 KURAPATI RAJA VARUN
 CHEDURI SURYA UMA SHANKAR
 ABSTRA
CT
FIFO is an approach for handling program work requests
from queues or stacks so that the oldest request is handled
first. In hardware, it is either an array of flops or read/write
memory that stores data from one clock domain and on
request supplies the same data to other clock domains
following FIFO logic. This project will detail one method
that is used to design, synthesize and analyse a safe FIFO.
 BEFORE WE ENTER
INTO…
 A FIFO refers to a FIFO design where data values are written to a FIFO
buffer from one clock domain and the data values are read from the same
FIFO buffer from another clock domain, where the two clock domains are
asynchronous to each other.
 FIFOs are used to safely pass data from one clock domain to another clock
domain.
 There are many ways to do FIFO design, including many wrong ways.
Here we will see one method that is used to design, synthesize and
analyse a safe FIFO.
 TEAM MEMBER
CO
           
 N T R I B- EMPTY
DHANUSH UTIO N FULL BLOCK MODULE
AND

 CHOWDAVARAPU DHANUNJAY- WRITE POINTER

 MAAKAM VENKATA SRI GAURAV- READ POINTER

 KURAPATI RAJA VARUN - POINTER BLOCK

 CHEDURI SURYA UMA SHANKAR - COUNTER

EMPTY AND FULL BLOCK :

Module 1: fifo_mem
EMPTY AND FULL BLOCK I/O:
 Data inputs are clk-clock, rst- reset ,rd-read and wr-write

 Data outputs are empty ,full,and output ref[3:0]fifo_cnt

 Input is 8 bit and out put is also 8 bit {input [7:0] data_in
, output [7:0] data_out
 Reg[7:0] fifo_ram[0:7]-- > in ram we are having 8
location and each location having 8 bit of data
 Assign -- > this key word is data flow modelling i.e
assignment operator.
EMPTY AND FULL BLOCK FUNCTIONALITY:

           
 This is the FIFO memory that is accessed by both
the write and read clock domains.
 This memory is most likely an instantiated,
synchronous dual-port RAM.
 Other memory styles can be adapted to function
as the FIFO queue.
POINTER BLOCK:

           
Module 2:
memory_array
  

POINTER BLOCK I/O:

           

 Wr_ptr <= (wr && !full) || (wr && rd) ? wr_ptr+1 :

wr_ptr -- > this means in these 2 cases if they are true
write will be increased. If they are false it will remain
same
 rd_ptr <= (rd && !empty) || (wr && rd) ? rd_ptr+1 :
rd_ptr -- > this means in these 2 cases if they are true
read will be increased, if they are false it will remain
same
 POINTER BLOCK
F U N C T I O N A L I T Y:
           
This is a simple synchronizer module, used to pass an n-bit
pointer from the read clock domain to the write clock
domain through a pair of registers that are clocked by the
FIFO write clock.
READ POINTER CODE:

           

Module 3: read_pointer
 WRITE POINTER AND READ POINTER I/O :

           
 In this inputs are wr- write and rd-read
 Outputs are full, empty
 In this case if-else loop is being used
 Fifo_ram[wr-ptr] <= data_in means data is
feeding into ram but location is fixed by wr_ptr
 Data_out <= fifo_ram[rd_ptr] means data is in
ram and in which location data is there shown by
rd_ptr
 READ POINTER FUNCTIONALITY
           
 This module encloses all of the FIFO logic that is
generated within the read clock domain. The read
pointer is a dual n-bit Gray code counter.
WRITE POINTER CODE:

           
Module 4: write_pointer
 W R I T E P O I N T E R F U N C T I O N A L I T Y:
           
 This module encloses all of the FIFO logic that is
generated within the write clock domain. The write
pointer is a dual n-bit Gray code counter.
COUNTER:

           
Module 5: Counter
COUNTER:

           
 Case()
 endcase -- > this is case statement starting and
ending
 {wr ,rd} -- > concatenation of write and read
 2’b00 : fifo_cnt <= fifo_cnt: -- > this means
write and read both are zero so count is equal to
count
 Fifo_cnt-1-- > count minus one
 Fifo_cnt+1-- > count plus one
COUNTER FUNCTIONALITY:

 Counter
            depends on the write and read functionalities
counter is output biased.

 It counts the values that are to be displayed.

 It keeps track of no. of data in the queue and issues

empty and full flag.
OUTPUT SCREENSHOT:

           
OUTPUT SCREENSHOT:

           
OUTPUT SCREENSHOT:

           
THANK YOU