Core of the embedded

system
 Core of embedded system
• Embedded systems are domain and application
specific and are built around a central core.
• The core of the embedded system fall into any one of
the following categories:
– General purpose and domain specific processors
• Micro-processors
• Micro-controllers
• Digital signal processors
– Application specific integrated circuits (ASIC)
– Programmable logic devices (PLD)
– Commercial off the shelf components (COTS)
General purpose and Domain specific Processors
Almost 80% of the embedded systems are microcontroller/ microprocessor
based.
Microprocessor – CPU capable of performing arithmetic as well as logic
operations with the combination of other hardware like memory, timers,
interrupt controller etc. for proper functioning.
•1971 - Intel 4004
– 4 bit processor
– 16 - 4bit General Purpose Registers
– Clock speed 740kHz
– 46 instructions
– 1K Data Memory, 4K Program Memory, 12 bit Program Counter
– Designed for old days calculators.
General purpose and Domain specific Processors
• 1972 - 4040
– 14 more instructions added to 4004
– 8K Program Memory
– Interrupt capabilities added to it.
• April 1972 - 8008
– Similar to 4004
– 14 bit PC
– Serves as a terminal controller
• 1974 - 8080
– First 8 bit microprocessor
– 16 bit address bus and 16 bit Program Counter
– 7 - 8 bit registers
– Commonly used in industrial control & other embedded appln’s.
• Motorola 6800 –
- Different architecture & instruction set compared to 8080.
General purpose and Domain specific Processors
• 1976 - 8085
– Upgraded version of 8080
- 2 newly added instructions
– 3 interrupt pins
– Serial i/o
– Clock generator and Bus controller circuits (built in)
– Power supply part modified to a single +5 supply

• 1976
- Zilog entered the microprocessor market (Z80)
– It is an improved version of 8080 (maintaining original arch.)
- Designed by Frederico Faggin (Ex-Intel Designer)
– 80 more instructions
– 8 bit data bus, 16 bit address bus and executes all instructions of
8080.
– Brought out the concept of register banking by doubling the
register set.
General purpose and Domain specific Processors
• Then 16, 32, 64 bit processors came in the place of 8 bit
microprocessor.
• The initial 2MHz clock is now GHz range.
• Intel, AMD, Free scale, IBM, TI, Cyrix, Hitachi etc.. are key players in
processor market.
• Different instruction set and system architecture are available for
microprocessor design.
– Harvard and Von-Neumann
Processors based on Harvard architecture contains separate buses for
program and data memories whereas Von-Neumann shares single
system bus.
– CISC and RISC- two common instruction set architectures for
processor design.
 General purpose (GPP)
vs.
Application specific instruction set processors (ASIP)
 Microcontrollers
• Highly integrated chip that contains
– CPU
– SFR, GPR
– RAM, ROM / FLASH
– Timers
– Interrupt control unit
– Dedicated i/o ports
• Superset of microprocessors and do independent
working.
• Cheap, cost effective, readily available in market
 Microcontrollers
1974
- TI's TMS 1000
– known as the 1st micro-controller
– TI followed the Intel's 4004/4040 design and added
some RAM, ROM & i/o support on a single chip.

1977
- Intel - MCS48 family
–8038HL, 8039HL, 8040AHL, 8048H, 8049H,8050AH

8048
- Intel's 1st micro-controller
- Used in the IBM-PC keyboards
- Inspiration is Fairchild F8 and goal of developing a low
cost and small size processor
- Harvard architecture
 Microcontrollers
• 1980’s - MCS51
– Intel's 8 bit micro-controller domain
– Almost 75% of the micro-controllers used in
embedded domain uses 8051 family based
controllers during 1980s to 1990s.
– 8051 processor core are used in more than
100 devices by more than 20 independent
manufacturers, under the license from Intel.
• PIC family micro-controller
– From microchip technologies
– High performance RISC processor complementing
the CISC features of 8051
 Microcontrollers
• Infineon, Freescale, Atmel, Maxim, Microchip etc..
are the key suppliers of 16 bit micro-controllers.
• Added more and more functionality like:
– SPI
– I2C
– USB
– ADC
– Networking capabilities etc..
• ARM - high processing speed micro-controller
families.
• The instruction set architecture of micro-controller
can be RISC or CISC
Microprocessors
Vs
Microcontrollers
 Digital Signal Processors
• Powerful special purpose 8/16/32 bit micro-processor.
• Designed specifically to meet the computational demands & power
constraints of today's embedded audio, video & communications
applications.
• DSP are 2 to 3 times faster than the general purpose microprocessor in
signal processing applications.
• This is because of the architectural difference b/w the two.
• DSP implements algorithms in h/w which speeds up the execution.
• General purpose processors implements algorithms in firmware & speed
of execution depends primarily on the clock for the processors.
• A typical DSP incorporates the following units:
– Program Memory, Data Memory, I/O units, Computational Engine.
• Ex: Audio / Video Signal Processing, Telecommunication and
Multimedia
• Ex: Blackfin Processors from Analog Devices – 32 bit RISC
RISC VS CISC
Harvard vs Von-Neumann Architectures
 Big Endian vs Little Endian
• Endiannes specifies the order in which the data is stored
in the memory in a multi-byte system.
• If word length is 2 byte then data can be stored in 2 ways

• Little Endian:
The lower order byte of the data is stored in memory at the
lower address & the higher order byte at the highest
address.

• Big Endian:
The higher order byte of the data is stored in memory at
the lower address & the lower order byte at the higher
address.
 Load and store operation

• Load- content of memory location loaded to a

register
• Store- stores the content of data from the
specified register to specified memory 
• E.g.. Add contents of memory locations x, y and
store the result in location z
▫ load R1,x
▫ load R2,y
▫  add R3,R1,R2
▫ store R3,z
 Instruction pipelining

• Conventional instruction execution –  fetch-

decode-execute
• Instruction pipelining refers to the overlapped
execution of instructions
• Processing speed can be increased
Application specific integrated circuits
• A microchip designed to perform a specific or unique application.
• It is used as replacement to conventional general purpose logic
chips.
• It integrates several functions to a single chip & there by reduces
the system
development cost.
• Consumes a very small area and there by helps in the design of
smaller systems
• ASIC can be pre-fabricated for a special application or it can be
custom fabricated.
• Profitable only for large volume commercial production.
 Programmable logic devices
• Logic devices provide specific functions can be classified
into 2 categories:
– Fixed & programmable
• Circuits in fixed logic devices are permanent
– They perform one function or set of functions.
– Once manufactured they can't be changed.
• Programmable logic devices offer:
– Customers a wide range of logic capacity, features,
speed & voltage characterizes & these devices can be re-
configured to perform any no. of function at any time.
 CPLD & FPGA
2 major type of PLD s.
• FPGA
– offer the highest amount of logic density, more features & the highest
performance.
- Offers built in h/w processors, clock management systems, device to device
signaling
– used in a wide variety of application ranging from data processing & storage to
instrumentation, telecommunication & DSP.
• CPLD
– offer much smaller amounts of logic density, up to about 10000 gates.
– offer very predictable timing characteristics & are therefore ideal for critical
control
applications.
―Usually requires low amount of power
―Very inexpensive
―Ideal for cost-sensitive, battery operated
―Ideal of portable applications such as mobile phones
 Advantages of PLD
• Offer customers much more flexibility during design
cycle.
• Do not require long lead time for production part.
• Allows customers to order just number of parts they
need, when they need them.
• Can be reprogrammed.
• Provides the ability to add new feature or upgrade the
products that are already in the field by simply
uploading a new programming file to the PLD via
internet.
 Commercial off-the shelf components
• COTS product are designed in such a way to provide easy
integration & interoperability with existing system
components.
• The COTS components itself may be developed around a
general purpose or domain specific processor or an ASIC or
PLD.
•E.g.- remote controlled toy car control units like RF circuitry
part, ADC , UV detectors etc.
•Readily available in the market and are cheap
•Developer can cut down development time
•Since no operational and manufacturing standards end user
should stick to a particular vendor for a particular COTs
•Manufacturer of the COTS component may withdraw the
product at any time
 Memory

• Memory
• Type of memory interface
• Memory shadowing
• Memory selection for embedded system
 Memory
• On-chip memory
• External memory(off-chip)

• ROM – Program storage memory(Non-

volatile)
 Masked ROM
• One time programmable device
•Pre programmed by the manufacturer
•Make use of hardwired technology for storing data
• Advantage
– Low cost (least expensive type)
– High volume production
• Different mechanisms used for the masking
process.
 PROM / OTP
• One time programmable memory (OTP) or PROM.
• It is not pre-programmed by the manufacturer.
• The end user is responsible for programming the device.
• It consists of nichrome or polysilicon wires used as fuses
arranged in a
matrix.
• It is programmed by a PROM programmer which
selectively burns the fuses according to the bit pattern to be
stored.
• The fuses which are not blown/burned represents a logic 1
and which are burned represents 0. So the default state is 1.
•Can not be reprogrammed and low cost solution for
commercial production.
 EPROM
• OTPs are not useful & worth for development purpose.
• Gives flexibility to re-program the same chip.
• Stores the information by changing the floating gate of a FET.
• Stored by using EPROM programmer which applies high
voltage to charge
the floating gate. The charge contained in FGMOSFET remains
unchanged
for long periods of time
• EPROM contains quartz crystal window for erasing the stored
information.
• If the window is exposed to UV ray for a fixed duration, the
entire memory
will be erased(20 – 30 minutes)
•Tedious & time consuming
 EEPROM
• Information can be altered by using electrical
signals.
• Can be reprogrammed in circuit.
• These chips include a chip erase mode & in this
mode they can be erased
in a few milli sec.
• It provides greater flexibility for system design.
• Limitation:
– Capacity is limited when compared with the
standard ROM
 FLASH
• Latest and most popular ROM technology.
• It is a version of EEPROM technology.
• It combines the re-programmability of EEPROM & high
capacity of
standard ROM s.
• FLASH memory is organized as sectors (blocks) or pages.
• Stores info- in an array MOSFET.
• Erasing of memory can be done at sector/page level
without affecting the other sector/page.
• Each sector/page should be erased before reprogramming
• Typical erasable capacity of FLASH is 1000 cycles.
 RAM
• It is a Data memory or Working memory.
• It is a direct access memory – access the desired
memory location without
traversing through the entire memory locations.
• RAM is volatile – power is turned off, data is destroyed

• RAM:
– SRAM
– DRAM
– NVRAM
 SRAM
• Stores data in the form of voltage
• They are made up of flip-flops
• Fastest form of RAM. Typical access time is 10ns
• Each bit is realized using 6 transistors
(6MOSFETs), 4 for latch part and 2 for access
control
• Fast in operation due to resistive networking and
switching capabilities
• Does not require refreshing
• Limitation:
– Low capacity
– High cost
 SRAM

A Typical SRAM Cell

Operation B B/ Word
Line
Write 1 0 1
Read 1 1 1
 DRAM
• Stores data in the form of charge.
•Made up of a MOSFET and a capacitor
• Advantage:
– High density
– Low cost
• Disadvantage:
–Since the information is stored as charge, it get
leaked of with time & to prevent this they need to
refreshed periodically.
– DRAM controllers are used for refreshing.
– Refresh operation is done periodically in ms
interval
• MOSFET act as gate for incoming & outgoing data
and capacitor acts as bit storage unit.
SRAM vs DRAM
 NVRAM
• It is a RAM with battery backup.
• It contains static RAM based memory & a minute
battery for providing supply to the memory in the
absence of external power supply.
• Memory & battery are packed together in a single
package.
• Used for non-volatile storage of results
•Life span is around 10 years
Ex: DS1744 from Maxim/Dallas
 Type of memory interface
Connection of memory to the processor can be of various
types
– Parallel interface
– Serial interface
• I2C
• SPI
• Serial interface – commonly used in EEPROM
• Memory density of a serial memory is usually expressed in
terms of “kilobits” (AT24C512 with capacity of 512 kilobits)
• For parallel interface memory is expressed in terms of
“kilobytes”.
 Memory shadowing
• Execution of a program from ROM is very slow
compared to RAM
• RAM access is three times as fast as ROM
– ROM access time is (120 – 200 ns)
– RAM access time is (40 – 70 ns)
• Shadowing of memory is a technique to solve the
execution speed problem in processor based system
• Eg: Manufacturers included a RAM behind the logical
layer of BIOS (Basic Input Output configuration) at its
same address as a shadow, to BIOS
• During boot up copy the BIOS to the shadowed RAM and
write protect the RAM then disable the BIOS reading
 Memory selection for embedded system
• Embedded system require PM (holds control algorithm or embedded OS &
applications) and DM (configuration data, look up table etc).
• Memory requirement is solely dependent on the type of the embedded system and the
application for which it is designed.
• Factors need to be considered when selecting the type & size of memory for embedded
system:
– Application
• (on-chip memory may be sufficient for designing the total system)
– system requirement and based on the type of processor
• For 8051 and PIC:
• For RTOS:
• 2 parameters for representing an memory
– Size of the memory
• Memory chip comes with standard size 4Kb, 8Kb, 16Kb etc.
• Address range supported by processor
– Word size of the memory
• no. of bits that can be read/write together 4, 8, 12, 16 etc.
• Word size should be matched for memory and processor.
 Memory selection for embedded system

• FLASH
– FLASH is the popular choice for ROM in embedded system
– FLASH comes with 2 major versions
• NAND FLASH
• NOR FLASH

• NAND FLASH
– High density, Low cost
– Non-volatile
– Can be used for storing programs & data
– Dose not support XIP (execute in place) – allows the execution of code memory
from ROM itself without the need for copying it to RAM.
• NOR FLASH
– Less density, Expensive
– It supports XIP technology.
– Can be used for storing boot-loader or for even complete program code.
 Memory selection for embedded system

• EEPROM
– It comes with parallel or serial interface.
– If the controller/processor supports serial
interface & the amount of data write and read to
and from the device is less, it is better to have a
serial EEPROM chip.
• Serial EEPROM is usually expressed in “bits” and
“kilo-bits” (512 bits, 1 Kbits, 2 Kbits etc.)
 Sensors And Actuators
• Sensors
– A sensor is a transducer device that converts energy from one form to
another for any measurement or control purpose.
― Changes in system environment or variables are captured by the sensors
connected to the input port of embedded system.

• Actuators
– Actuator is a transducer device (mechanical or electrical) which converts
signal to corresponding physical action (motion).
― ES designed for controlling purpose produce changes in controlling
variable to bring the controlled variable to desired value, which is achieved
through actuators connected to the output port of the system.

• I/O Subsystem
– The i/o subsystem of the embedded system facilitates the interaction of
the embedded system with the external world through sensors and
actuators. But they may be connected through signal conditioning and
translating systems.
 EXAMPLES

• LED
• 7 segment display
• Optocoupler
• Stepper motor
• Relay
• Piezo-buzzer
• Push button switch
• Keyboard
• PPI
 LED
• Output device used for visual indication in any embedded system.
• Indicates the status. Eg: device ON, Battery low, Charging of battery.
• P-n junction diode (having anode connected to +ve terminal of
supply voltage & cathode to –ve terminal of supply voltage).
Two ways of interfacing LEDs to the port pin of processor.
Method1: Anode of LED directly connected to the port pin and port
drives LED.
Port pin sources current to LED when the port pin is at logic 1.
Method2: Cathode of LED is connected to port pin of processor and
anode to the supply voltage through current limiting resistor.
• LED is turned ON when the port pin is at logic 0.
• Brightness of the LED depends on the maximum current the port
can source if connected directly. Hence in this method, current is
directly supplied by power supply and port pin acts as sink for
current.
 LED

Method 1 Method 2
 7-Segment Display

• An output device for displaying alpha numeric characters.

• It contains 8 LED segments arranged in a special form.
• In it 7(A-G) are used for displaying alpha numeric character &
1(H) for representing 'decimal point'. Two configurations
– Common anode
– Common cathode
• Depending on configuration, LEDs anode/cathode are
connected to port with A segment to least significant port pin and
DP to most significant one.
• Current flowing through each segment must be limited to the
max. value supported by LED unit(20mA). Usually done through
a current limiting resistor.
• Ex: Public telephone call monitoring devices.
7-Segment Display
 Optocoupler

• A solid state device to isolate 2 parts of a circuit.

• Combines an LED and photo transistor in a single
package.
• Used for suppressing interference in data
communication, circuit isolation, high voltage
separation etc.
• Can be used in input or output circuits.
• Available as ICs. Ex: MCT2M IC
 Stepper Motor
• Electro-mechanical device that produces discrete rotation in
response to the dc voltage applied to it.
• Differs from dc motor(continuous rotation on dc voltage).
• Ex: Printers, robot control systems.
• Based on the coil winding arrangement, Two phase stepper
motor is classified in to:
– Unipolar
• Contains 2 winding per phase.
• Direction of rotation is controlled by changing
the direction of current flow.
– Bipolar
• Contains 1 winding per phase.
• For reversing the motor rotation the current
flow through the winding is reversed
dynamically.
Stepper Motor
Stepper Motor
Stepper Motor
 Stepper Motor
• Stepping the stepper motor can be implemented in different ways by
changing the sequence of activation of the stator windings
• Different stepping modes:
– Full step
• Both the phases are energized
simultaneously.
– Wave step
• Only one phase is energized at a time
& each coils of the phase is energized
alternatively.
– Half step
• Combination of wave & full step.
• It has the highest torque and stability.
 Stepper Motor
• Rotation of the stepper motor can be reversed by reversing the
order in which the coil is energized.
• 2 phase stepper motors are the popular choice for embedded
applications.
• The current requirement for stepper motor is little high & hence
the port pins of a micro-controller may not be able to drive them
directly.
• Also supply voltage required to operate stepper motor varies.
• So depending on the current and voltage requirements, special
driving circuits are required to interface the stepper motor with
micro-controller.
• Eg: ULN2803, ULN2003 etc.
Stepper Motor
 Relay
- Electromechanical device which acts as a dynamic
path selector for signals and power
- Contains a relay coil made of insulated wire on a
metal core and a metal armature with one or more
contacts
- Works on the principle of electromagnetics
- Relay Configurations :
– Single pole single throw normally open
– Single pole single throw normally closed
– Single pole double throw
 Relay

- Free wheeling diode.

Used to free-wheeling the
voltage produced in the
opposite direction, when
the relay coil is de-
energized.
 Keyboard
• Input device for user interfacing.
• Switches - Used when the no. of keys required are limited
and are directly connected to the port pin.
• When more keys are required, it is wastage of port pins and
hence matrix keyboards are solution.
• Keyboards are organized in a matrix of rows and columns
• The CPU accesses both rows and columns through ports
• Therefore, with two 8-bit ports, an 8 x 8 matrix of keys can
be connected to a microprocessor
• When a key is pressed, a row and a column make a contact.
Otherwise, there is no connection between rows and columns
 Keyboard
-For detecting a key press,
scanning technique is used
- Each row is pulled low and the
corresponding columns are read
- The row is pulled high and the
next row is pulled low and the
columns corresponding to it are
read and so on till all the rows
are read.
-When the row is pulled low and
if a key connected to it is
pressed, reading the column will
to which the key is connected
will give logic 0
-It has debounce issues
- Two prevention techniques
- Hardware debounce
- Software debounce
Programmable Peripheral Interface (PPI)

• PPI – used for extending I/O

capabilities of processors.
• 8255A is a popular device for 8
bit processors / controllers
•Consists of 24 I/O pins
grouped either as three 8-bit
parallel ports (Port A, B, C) or
two 8-bit ports (Port A, B) and
two 4-bit ports (Port C)
Programmable Peripheral Interface (PPI)
8255
• PA0 - PA7 (8-bit port A)
– Can be programmed as all input or output, or all bits as bidirectional
input/output
• PB0 - PB7 (8-bit port B)
– Can be programmed as all input or output, but cannot be used as a
bidirectional port
• PC0 – PC7 (8-bit port C)
– Can be all input or output
– Can also be split into two parts:
• CU (upper bits PC4 - PC7)
• CL (lower bits PC0 – PC3)
– each can be used for input or output
– Any of bits PC0 to PC7 can be programmed individually
These Ports are configured by manipulating the control register of 8255A
Programmable Peripheral Interface (PPI)
8255
Programmable Peripheral Interface (PPI)
8255
Programmable Peripheral Interface (PPI)
8255

• Mode 0, simple I/O

– Any of the ports can be programmed as i/p or o/p
– All bits are out or all are in
• Mode 1
– Port A and B can be used as input or output ports with
handshaking capabilities
– Handshaking signals are provided by the bits of port C
• Mode 2
– Port A can be used as a bidirectional I/O port with
handshaking capabilities provided by port C
– Port B can be used either in mode 0 or mode 1
• 4. BSR (bit set/reset) mode
– Only the individual bits of port C can be programmed
Programmable Peripheral Interface (PPI)
8255
Programmable Peripheral Interface (PPI)
8255
 Communication Interface
• For communicating with various subsystems of the embedded system
and with the external world.

• For an embedded product, the communication interface can be viewed in

two different perspectives:
– device/board level communication interface (on-board
communication interface)- interconnection of components
within a product.
Ex: I2C, SPI, UART, 1-wire interface
– Product level communication interface(external)-
interconnection between embedded system and other devices or
modules.
Ex: Infrared, Bluetooth, Wireless LAN, RF, GPRS – wireless
Ex: RS-232/422/485, USB, Ethernet,…- wired
 On-board communication interface

Inter Integrate Circuit (I2C)

• Developed by Philips Semiconductor in 1980 s.
• Synchronous bi-directional half duplex.
• 2 wire serial interface bus:
– SDA(Serial Data), SCL(Serial Clock)
SCL – generates synchronous clock pulses
SDA – transmits serial data across devices.
•Shared bus system – I2C devices can be connected that can act as
Master & Slave
•Master – controls the communication by starting and stopping
transfer, generating sync pulses
•Slave – waits for the commands and responds.
• Both bus lines should be pulled up to the supply voltage for
proper functioning.
• Address of the I2C devices assigned at the time of design.
 Inter Integrated Circuit (I2C) Bus
- Bus interface built around
input buffer and open
drain or collector transistor
-When bus is in idle state,
transistor will be in
floating state and output
line in high impedance
state
-For proper operation both
lines (SDL & SCL) should
be pulled to Vcc
-Address of I2C is assigned
by hardwiring address lines
of the device to desired
logic level
 Inter Integrated Circuit (I2C) Bus
• Sequence of operations for communicating with an I2C slave device
are:
– 1. master pulls clock (SCL) to high
– 2. Master pulls SDA to low. (start condition)
– 3. Master sends address (MSB first) of slave to which it
communicates and data is valid during high state of SCL.
– 4. Master send R/W bit, 1 for read and 0 for write.
– 5. wait for acknowledgment from the slave whose address
is sent along with R/W
– 6. slave giving acknowledgment on SDA
– 7. 8 bit data transferred depending on R/W bit
– 8. acknowledgment transmitted.
– 9. stop
 Inter Integrated Circuit (I2C) Bus

3 different data rates:

– Standard mode: up to 100kbps
– Fast mode: up to 400kbps
– High speed mode: up to 3.4Mbps
 Serial Peripheral Interface (SPI)
• Introduced by Motorola
• Synchronous bi-directional full duplex
• 4 wire serial interface bus.
– MOSI – Master Out Slave In– signal line carrying data from master to slave.
(Slave Input/Slave Data – SI / SDI)
– MISO – Master In Slave Out - signal line carrying data from slave to master.
(Slave Output – SO/SDO)
– SCLK – Serial Clock - signal line carrying clock signals.
– SS – Slave Select (active low) - signal line for slave device select.
• Single-master multi-slave system.
• Master device – generates clock signal, selects the slave by asserting slave
device SS=0.
• MISO of all other slaves floats at high impedance state.
Serial Peripheral Interface (SPI)
 Serial Peripheral Interface (SPI)
• Data transmission through SPI is fully configurable – registers for
configuration.
• Having control register for holding configuration :
– master/slave selection
– Baud-rate selection
– Clock control
– LSB/MSB transmits first (configurable)
• Status register – status of various conditions for transmission and
reception
• SPI works on the principle of shift-register.
• Master(MOSI/MISO) and slave(MISO/MOSI) contains shift register to
transmit and receive.
•Master-Slave form a circular buffer
• Size of the shift-register is device dependent
– Normally it is a multiple of 8
Advantage: Suitable for applications requiring data transfers in streams
Disadvantage: No acknowledgements.
 Universal Asynchronous Receiver Transmitter
• Asynchronous
• No clock signal for synchronization.
• Relies on predefined agreement between transmitter and receiver
• Settings(baud rate, stop bits, start bit, parity bits and flow
control) must be identical to both TX and RX.
• For data byte, start bit is added first and stop bit at the end with
LSB after the start bit
• Start bit
- Informs the receiver that a data byte is about to arrive.
– Data(LSB)
– Stop bit
• Receiver polls its Rx line as per baud rate settings.
• UART also supports hardware handshaking for controlling the
data flow.
• Eg: 8250
Universal Asynchronous Receiver Transmitter
 1-wire interface
• Asynchronous half-duplex
• Maxim Dallas Semiconductor
• Having single wire – DQ
• Allows power to be sent along the signal wire
• Follows master-slave model(single master and
multiple slave)
• 1-wire device contains globally unique identifier
– 64bit identifier no. stored within it.
• Used to address individual devices present on bus.
– Identifier has 3 parts.
• 8 bit family code.
• 48 bit serial no.
• 8 bit CRC (computed from first 56 bits).
1-wire interface
 1-wire interface

• The sequence of operation for communication are:

– 1. master device sends a “reset” pulse on the bus.
– 2. slave device present on the bus responds with
“presence” pulse.
– 3. master sends a ROM command(net address
command followed by the 64-bit address of the device)
to which it wishes to communicate.
– 4. master sends a read/write function command to
read/write the internal memory of the device.
– The master initiates the read data/write data from/to
the device.
 1-wire interface
• All the communication is master initiated.
• Communication over the 1-wire bus is divided into time
slots of 60 micro-seconds.
• Reset pulse:
– Occurs 8 time slots.
– Pulling the bus LOW for 8 time slots (480
microseconds)
• Slave responds with a “Presence” pulse if present and
ready to communicate:
– Within 60 micro seconds of the release of the “reset” by
pulling the bus LOW for a minimum of 1 time slot.
 1-wire interface

• Writing a bit 1:
– Master pulls the bus for 1-15 micro seconds & then
releases the bus for the rest of the time.
• Writing a bit 0:
– Master pulling the bus for 1-2 time slots (60-120
microseconds).
• Read a bit:
– Master pull the bus LOW for 1-15 micro seconds.
– If slave want to send 1 in response to the read request :
• It releases the bus reset of the time slot.
– If slave want to sent 0:
• It pulls the bus LOW for rest of the time slot.
 Parallel interface
• Normally used for communicating with peripheral devices which are
memory mapped to the host of the system.
• Host processor contains parallel bus and is directly connected to the
device that supports parallel bus.
• Controlled by control signals.
– Read / write
– Device select
Devices are memory mapped to processor and address range is assigned
to it.
• Address decoder can be used for generating the chip select signal for
device.
– When the address selected by the processor is within the range assigned
for the device, the decoder circuit activates the chip select.
• Processor then can read or write from the device by asserting the
corresponding control line
• Normally host processor initiated, devices can initiate through
interrupts.
• Data bus width(4bit, 8bit, 16bit, 32bit, 64bit etc.) determines width of
interface.
• Eg: ADC
Parallel interface
Serial vs Parallel Data Transfer
 External communication interface
RS232 – Recommended Standard Number 232, Recommendation C
from Electronic Industry Association
- standard by which two serial devices communicate
• Full duplex, Wired, Asynchronous serial communication interface developed by
EIA using standard TTL / CMOS logic
• Logic 0 (space): represented with voltage between +3 & +25v.
• Logic 1 (mark) : represented with voltage between -3 & -25v.
• Supports different types of handshaking and control signals.
• RS232 supports 2 different type of connectors:
– DB9 , DB25 (obsolete)
• Standard baud-rates: (20Kbps as per industry standards)
– 300bps, 1200bps, 2400bps, 4800bps, 9600bps,11.52kbps, 19.2kbps etc.
• Maximum operating distance is:
– 50 feet at highest supported baud-rate.
• point to point communication interface (Not suitable for multi-drop Commn.)
. Devices involved are called Data Terminal Equipment (DTE) or Data
Communication Equipment (DCE)
Level converter
• In embedded s/m requires level translator to convert UART to RS232.
• MAX232
External communication interface
 External communication interface

• TxD: This pin carries data from the computer to the serial device (DTE)
• RxD: This pin carries data from the serial device (DCE) to the computer
• DTR: DTR is used by the computer to signal that it is ready to communicate
with the serial device like modem. In other words, DTR indicates to the
modem that the DTE (computer) is ON.
• DSR: Similar to DTR, Data set ready (DSR) is an indication from the
modem that it is ON.
• DCD: Data Carrier Detect (DCD) indicates that carrier for the transmit data
is ON.
• RTS: This pin is used to request clearance to send data to a modem
• CTS: This pin is used by the serial device to acknowledge the computer's
RTS Signal.
 External communication interface

RS422 (for differential data communication)

• Supports data rate up to 100kbps.
• Distance up to 400 ft.
• The same RS232 connector is used at the device end & an
RS232 to RS422 converter is plugged in the
transmission line & reverse operation in the receiver
side.
• Supports multi-drop communication(With 1 transmitter
device & receiver device up to 10)
• RS485:
– Enhanced version of RS422 & supports multi-drop
communication with up to 32 devices.
– Uses addressing mechanism to identify devices.
 USB
Universal Serial Bus – wired high speed communication
medium
• 1st version USB released in 1995.
• USB com. s/m follows:
– Star topology
– USB host at the center
– One or more USB slave peripheral devices connected to it.
– Supports connections up to 127.
• USB transmits data in packet format and is host initiated.
.USB host controllers controls the communication b/w host and
slaves.
• Different Standards for implementing the USB host:
– Open host control interface (OHCI)
– Universal host control interface (UHCI)
 USB
USB Topology
 USB

• USB cable: up to 5 meters

• 2 type of connectors:
– Type A: for upstream connection (connection with host)
– Type B: for downstream connection (connection with slave)
– Both having 4 pins:
1. Vbus – carries power(5v)
2. D- differential data carrier line
3. D+ differential data carrier line
4. GND
• For data transmission –
– uses differential voltage.
– It improves noise immunity.
• Power supply: It can supply 500mA at 5V.
 USB
• Each USB device contains:
– Product ID (PID)
– Vendor ID (VID)
• Supports 4 types of data transfer:
– Control – used by USB system software for query, configure & issue
commands
to the USB device
– Bulk -for sending block of data. Ex: data transfer to printer from PC.
– Isochronous –Data transmitted as streams. For real time data communication,
does not support error checking & re-transmission. Ex: Medical equipment
– Interrupt-for transmitting small amount of data. Eg: mouse, keyboard etc.
• Supports 4 different Data rates:
– Low speed -1.5Mbps -defined by USB 1.0
– Full speed -12Mbps -defined by USB 1.0
– High speed -480Mbps -defined by USB 2.0
– Super speed-4.8Gbps -defined by USB 3.0
 IEEE 1394 (Firewire)
• Wired, isochronous high speed serial Communication bus
• Also known as High Performance Serial Bus (HPSB)
• Research on this started by apple and coined by IEEE
• Known with different names
• i.LINK by Sony; Lynx by texas instruments etc
• Supports Tree Topology
• Supports Peer to Peer and Point to Multi-Point communication
• Supports upto 63 devices
• Data rates of 400 to 3200 Mbps
• Uses differential data transfers along twisted pair cables and increases noise immunity
• Supports 3 types of connectors
• 4 pin. 6 pin (alpha connector) and 9 pin (beta connector)
• 6 pin and 9 pin can provide power to external devices in the range of 24 to 30v
 IEEE 1394 (fire-wire)
Pin name pin no. pin no. pin no.
4 pin 6 pin 9 pin
• Power _ 1 8
• GND _ 2 6
• TPB- 1 3 1
• TPB+ 2 4 2
• TPA- 3 5 3
• TPA+ 4 6 4
• TPA(s) _ _ 5
• TPB(s) _ _ 9
• NC _ _ 7
 IEEE 1394 (Firewire)
• Two differential data transfer lines A and B per connection
• Best interface connector for Digital Cameras, Camcorders, Scanners for
Desktop PC’s
• Doesn’t require a host for communicating between devices
• Data rate is higher than USB 2.0
• Implementation is much costlier than USB
 IrDA (infrared)
• Serial, half-duplex, line-of-sight based wireless communication medium.
• IrDA support:
– Point to point
– Point to multi-point
- used infrared waves of electromagnetic spectrum.
• Range: 10cm – 1m
– But range can be increased by increasing transmitting power of IR
• Data rate: 9600bps – 16Mbps
• Depending up on the speed, it is classified as:
– Serial IR (SIR) : 9600bps to 115.2kbps
– Medium IR (MIR) : 0.576Mbps - 1.152Mbps
– Fast IR (FIR) : up to 4Mbps
– Very fast IR (VFIR) : up to 16Mbps
– Ultra fast IR (UFIR) : up to 100Mbps
 IrDA (infrared)

• Infra red data association is the regulatory body for

defining and licensing the specification for IR
communication.
• IrDA communication involves transmitter(LED) and a
receiver(Photodiode).
• For bidirectional data transfer, transceiver is present, but
for unidirectional transfer like TV remote, either of them is
present.
• It has two essential parts
▫ Physical link – responsible for transfer of data between the devices.
▫ Protocol - defines the rules of communication. Contains the implementations
for PHY, MAC (Media Access Control) and LLC (Logical Link Control)
▫ Used for file exchange and data transfer in low cost devices before Bluetooth’s
existence.
 Bluetooth (BT)
• Low cost, low power, short range wireless technology for voice and
data communication.
• Proposed by Ericsson
• Operates at 2.4GHz of RF spectrum and uses Frequency Spread
Spectrum Hopping.
• Supports data rate up to 1Mbps.
• Range is approximately 30 ft.
• It has 2 essential parts
– Physical link part - responsible for physical transmission
– Protocol part - defining the rules of communication
• Each Bluetooth device will have a 48bit unique identifier no.
• It follows packet based data transfer.
• Supports
– Point to point(master and slave)
– Point to multi-point(Piconets) – Max. 7 devices
 Bluetooth (BT)

Bluetooth standards:
• GAP (Generic Access Profile)
– Defines the requirements for detecting a Bluetooth
device & establishing a connection with it.
• SPP (Serial Port Profile)
– For serial data communication.
• FTP (File Transfer Protocol)
– For file transfer b/w devices.
• HID (Human Interface Device)
– For supporting human interface devices like keyboard,
mouse etc.
 Wi-Fi
Wireless Fidelity
• Wi-Fi follows the IEEE 802.11 standard.
• Intended for n/w comm. & supports IP.
• Each device is identified by IP address, unique in the
network and communicates based on intermediate
agent called WI-FI Router/WAP (Wireless Access
Point) that restricts the access to network.
• Wi-Fi operates at 2.4GHz or 5GHz of radio frequency
and coexist with other ISM band devices.
• When the Wi-Fi radio of the device is ON,
– searches the available Wi-Fi n/w s & lists out the
service set identifier (SSID).
– If the n/w is security enabled, a password may be
required to connect to the SSID.
 Wi-Fi
WI-FI NETWORK
 Wi-Fi
• Wi-Fi employs different security mechanisms:
– WEP (Wired Equivalency Privacy)
– WPA (Wireless Protected Access)
• Supporting data rate:
– 1Mbps – 150Mbps depending up on the
Standards (802.11 a/b/g/n)
& access / modulation method
• Depending upon the antenna & usage location
(indoor/outdoor) Wi-Fi offers range of 100 –
300 ft.
 ZigBee
• Low power, low cost, wireless n/w communication protocol.
• Based on IEEE 802.15.4 standard.
• Targeted for low data rate applications for wireless personal
area networking (WPAN)
• Supports robust mesh networking to allow messages to travel
through multiple paths to get through the nodes.
• Operates at unlicensed bands of radio spectrum
– 2.4 – 2.484GHz
– 902 – 928MHz
– 868 – 868.6MHz
• Distance : 100m
• Data rate : 20 – 250kbps.
• ZigBee device falls under any one of the following:
– ZigBee coordinator (ZC) / N/w coordinator
– ZigBee Router (ZR) / Full Function Device (FFD)
– ZigBee end device (ZED) / Reduced Function Device (RFD)
ZigBee
 ZigBee
• ZigBee coordinator – Root of the network and is
responsible for initiating the network and stores
information about network.
• ZigBee Router – Responsible for passing information
from device to device.
• ZigBee end device – Contains ZigBee functionality for
data communication. It can talk only with ZR or ZC and
cannot transfer data from one device to other.
Applications:
Home and industrial automation
Energy management
Home security
Patient tracking
Logistics and asset tracking …….
 GPRS
• Communication technology for transferring data over a mobile
communication N/w like GSM.
• Data is sent as packets.
• Transmitting devices splits the data into several related
packets and the receiving end reconstructs by combining the
data packets.
• Transfer rate : maximum 171.2kbps.
• GPRS communication divides the channel into 8 time slots &
transmits data over available channels.
• GPRS supports : IP, Point to Point, X.25 protocols.
• Mainly used by mobile enabled embedded devices.
• Device should support the necessary:
– GPRS modem & GPRS radio.
• New generation data communication tech- are
– EDGE
– HSDPA(high speed down-link packet access)
These offers higher bandwidth for communication.