Introduction

 An Embedded Processor is a special purpose processor which

when used in an embedded system design can perform only
dedicated one or few tasks.
 It differs from the normal general purpose computers like servers
and personal computers in the sense that later can be programmed
to perform diverse ( many & different ) range of tasks.
 Why design an embedded when the general purpose can serve the
same purpose?
 Cost reduction

 Energy efficiency

 Tailored (simple) for almost anything depending upon

requirements such as specialized Signal Processing capability

 Size reduction (Such as Smart Dust in MEMS/mote)

08/23/21 1
 Smart Dust vs MEMs

 Smartdust is a term used to describe groups of very small

robots used for monitoring and detection.
 Currently, the scale of Smartdust is rather small, with single
sensors the size of a deck of playing cards, but the hope is to
eventually have robots as small as a speck of dust.
 Individual sensors of Smartdust are often referred to as motes
because of their small size.
 These devices are also known as MEMS, which stands for
microelectromechanical sensors.

08/23/21 2
 Introduction
 Embedded Systems perform dedicated tasks, and put particular
requirements on the processors controlling them
 These functionality wise differences even become more diverse
within the embedded systems as clear from the following some of
the applications
 Portable Devices:
PDA’s, Digital Cameras, MP3 players, Mobile phones
 Automotive:
Automobile engine control systems, Tracking systems,
Functionality check systems
 Networking:
Ethernet switches, routers
 Medical Equipment:
Medical Imaging and video of inside of body / Ultrasound
 Industrial Controls:
Nuclear Reactor Control, Lathe Machine Controls etc

08/23/21 3
 Digital Camera Functional Block Diagram

08/23/21 4
 GPP vs Embedded Processors
 Functionality wise differences in the embedded
applications/processors results in several architectural
differences between the embedded processors and general
purpose processors.
 Control Unit

 CPU Register files

 CPU cores (multiple)

 On-Chip Caches

 On-Chip peripherals

 Instruction Set Architecture

 Pipeline Requirements

 Arithmetic Computation

08/23/21 5
 Embedded Processing Areas

The latest application and research areas for embedded

processor architectures include:
 Wearable Computing

 Ubiquitous Computing

 System On Chip

 Multiprocessor System On Chip

 Network on Chip

08/23/21 6
 Comparison of GPP and Embedded
Processor

Functional Block Diagram of the

Functional Block Diagram of the
General purpose CISC processor.
embedded processor

In addition to differences above

the instruction set architecture is also different
08/23/21 7
 Embedded Processor Architecture

Factors influencing embedded processor architecture:

Real-time processing:
Some computation must be done within a certain time frame, or
else the system would fail. Consider the following example:
A system fetching/compressing/sending voice data
Timing constraint:
It must fetch the voice data after every specified interval, it
must compress/decompress/send the audio data within a
certain time frame (e.g. 22.5 msec in a MELP algorithm), and
then transmit it to a remote end or human ear in that
particular time, or else there may be un-acceptable voice quality
degradation.

08/23/21 8
 Embedded Processor Architecture
The real-time processing can further be divided into two categories:
 Hard real-time system:

It is the one in which there is an absolute maximum time to complete

certain processing.
 For example voice compression/processing must complete within a
certain dead line always.
 Dynamic branch predictions and cache mechanisms of the general
purpose processors are advantageous for the non-real-time
applications, but would result in a catastrophe in the hard real-time
requirements.
 Soft real-time system:
It is the one in which the average time of a particular task may
exceed by a limited time
 For example nullifying the effect of the varying inter-arrival times of
voice packets through jitter buffers over a digital voice communication
link.

08/23/21 9
 Embedded Processor Architecture
signal processing
 DSPs are used for filtering, transformation etc using

functions like Multiply and Accumulate etc

 They usually require many registers, memory

blocks, multipliers and other arithmetic units

08/23/21 10
 Embedded Processor Architecture

 Power consumption:
(i) These are mostly battery operated systems so long
operation life before recharging.
(ii) virtually no special cooling arrangement required decreasing
cost as well as size
(iii) least instruction + more work = least power
consumption
 Limited memory:
The memory size is always less in an embedded application as
only few or only one program would be required to run on it. This
factor is determined by many things.
(i) size would become smaller
(ii) Overall system cost would be reduced
(iii) System would consume much less power

08/23/21 11
 System on chip (SoC)

 SoC Integrates all components of a computer or other

electronic system into a single integrated circuit (chip).
 It may contain digital, analog, mixed-signal, and often
radio-frequency functions – all on one chip.
 Typical application of SOC is embedded systems like
Microwave oven controller.
 SiP (System in Package) contains a SoC in an
application package to perform intelligent functions

08/23/21 12
General Purpose Processors

Data Path consists of the

circuitry for transforming data
and for storing temporary data.
It contains ALU and Register File

13
 Single-purpose processors
Digital circuit designed to execute exactly
one program e.g. coprocessor, accelerator
or peripheral
Features
 Contains only the components needed to

execute a single program

 No program memory

Benefits
 Fast

 Low power

 Small size

 Small Datapath

08/23/21 14
 Digital Signal Processor

 It is a single purpose processor that is highly

optimized to process large amounts of data
 The source for such data may be a digital camera,
voice packet or an audio clip
 It usually contains many registers, memory blocks,
multipliers and other arithmetic units
 DSPs are used for filtering, transformation etc using
functions like Multiply and Accumulate etc

08/23/21 15
 Application-specific processors
 Programmable processor optimized for a particular
class of applications having common characteristics
 Compromise between general-purpose and single-
purpose processors
Features
 Program memory

 Optimized datapath

 Special functional units

Benefits
 Some flexibility

 Good performance, size and power

08/23/21 16
 Full-custom IC

All layers are optimized for an embedded system’s

particular digital implementation like:
 Placing transistors

 Sizing transistors

 Routing wires

Benefits
 Excellent performance, smallest size, low power

 Drawbacks

 High Non-Recurring Engineering (NRE) cost (e.g.,

$300k), long time-to-market, high risk

08/23/21 17
 Gate Array

Features
 Lower layers are fully or partially built

 Designers are left with routing of wires and placing

blocks
Benefits
Good performance, good size, less NRE cost than a
full-custom implementation (perhaps $10k to $100k)
Drawbacks
Still require weeks to months to develop

08/23/21 18
 Standard Cell

Features
Instead of designing the actual silicon, the designer
uses pre-built “blocks” that have already been tested
and proven.
Benefits
Good performance, good size, less NRE cost than a
full-custom implementation (perhaps $10k to $100k)
Drawbacks
Still require weeks to months to develop

08/23/21 19
 PLD (Programmable Logic Device)

All layers already exist

 Designers can purchase an IC

 Connections on the IC are either created or

destroyed to implement desired functionality

08/23/21 20
 PLD (Programmable Logic Device)

Field-Programmable Gate Array (FPGA) very popular

Benefits
 Low NRE costs, almost instant IC availability

Drawbacks
 Bigger, expensive (perhaps $30 per unit), power

hungry, slower

08/23/21 21
 Independence of processor & IC technologies

Basic tradeoff
 General vs. custom

 Processor technology or IC technology

08/23/21 22
 Software Development

 The software development process can be

represented by lifecycle, also called a waterfall
or linear incremental model.
 Four stages of developing an embedded system
 Analysis

 Design

 Implementation

 Maintenance

08/23/21 23
 User Interface

 Embedded systems range from

 No user interface at all

 Dedicated only to one task

 Full user interfaces similar to

desktop operating systems in

devices such as PDAs.

08/23/21 24
 Challenges and Opportunities

 Diversity of operating environments and platforms

poses a real challenge in deploying software across
multiple platforms and configurations.
 Portability and reusability of the applications.
 Open Software Development i.e. Use of embedded
operating systems providing POSIX interface
facilitates

08/23/21 25
 Implementation Issues

 Computing performance
In a real time embedded control environment is not simply an
instructions- per-second rating.
 While raw computational performance is important, other

factors which are vital to system performance include interrupt

response characteristics, context switching over head, and I/O
performance.
 Since real time tasks are characterized by frequent, often

unpredictable events, the performance of a processor at

handling interrupts is crucial to its suitability for real time
processing.
 Since a control application usually involves a reasonable

amount of communication with the outside world (such as

reading sensors and activating control circuits), good I/O
performance is also important.
08/23/21 26
 Implementation Issues:

 The same resource must be shared between different

tasks.
 Sharing

As a result of this competition for the CPU use, the

timing of the tasks is not fully determined and the
time delays should be taken into account.
 Alternative control algorithms should be ready to get
the control of the process.
 Adaptation:

Working in a changeable environment, the control

goals and options may change and the control
algorithms should be adequate to new scenarios.

08/23/21 27
 Implementation Issues:


Working conditions, such as priority, allocated time and
memory or signals availability may change.
 Thus, complexity, structure and basic properties of

the control system will change.

 Variable delays should be considered.
 The synchronicity of signals cannot be ensured

anymore.
 Validation and certification.
 Any embedded control system should be proved to be

reliable and safety operation should be ensured.

08/23/21 28
 ES development methodology

 Classical development was done through separate

hardware and software developer teams who
integrated their work towards the end which lacked in
desired optimization levels and turn around time etc.
 Recent trend is to use a Unified view of the design
process for Hardware and Software
 Hardware synthesis tools have changed the role of
hardware designers essentially to write sequential
programs through HDL
 Hardware / Software Co-Design is a field that
emphasizes a unified view of hardware and software
for which synthesis tools and simulators are used

08/23/21 29
 Unified View of Design Process

Co Design Ladder
08/23/21 30
 Embedded Systems
Instructor: Engr. Muhammad Musa

Lecture # 2
Chapter # 6
Embedded System Design
Vahid / Givargis
 Bus Interfacing Techniques
 Interfacing basics
 Microprocessor interfacing
 I/O Addressing

 Interrupts

 Direct memory access

 Arbitration
 Hierarchical buses
 Protocols
 Serial

 Parallel

 Wireless

08/23/21 32
 Introduction

 Embedded system functionality aspects

 Processing
 Transformation of data
 Implemented using processors
 Storage
 Retention of data
 Implemented using memory
 Communication
 Transfer of data between processors and memories

 Implemented using buses called interfacing

08/23/21 33
 What is a Bus

 A bus is a set of physical

connections (cables) which can be
shared by multiple hardware
components in order to
rd'/wr
communicate with one another. Processor Memory
enable

addr[0-11]

data[0-7]

bus
bus structure

08/23/21 34
 Timing Diagrams

 Most common method for describing a communication protocol

 Time proceeds to the right on x-axis Sequential
 Control signal:
 May be active low or high
 Data signal: not valid or valid
 Setup Time: Time before the state is stable
rd'/wr rd'/wr

enable enable

addr addr

data data

tsetup twrite
tsetup tread
read protocol write protocol

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 35

 Basic protocol concepts: Control methods
Asynchronous or state driven (Request vs Request Acknowledge)
Master Servant Master req Servant
req
ack

data data

req 1 3
req 1 3
data 2 4 ack 2 4
data
taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant puts data on bus and asserts ack
3. Master receives data and deasserts req 3. Master receives data and deasserts req
4. Servant ready for next request 4. Servant ready for next request

Strobe
StrobeProtocol
protocol Hand Shake
HandshakeProtocol
protocol

Also Try similar protocol when master Sends Data to Slave

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 36
 A strobe/handshake compromise
Asynchronous or state driven with Wait Line
Master req Servant

wait

data

req 1 3 req 1 4
wait wait 2 3
data 2 4 data 5
taccess taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant can't put data within taccess, asserts wait ack
(wait line is unused) 3. Servant puts data on bus and deasserts wait
3. Master receives data and deasserts req 4. Master receives data and deasserts req
4. Servant ready for next request 5. Servant ready for next request

Fast Response
Fast-response case Slow Response
Slow-response case

Also Try similar protocol when master Sends Data to Slave

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 37
 Microprocessor interfacing: I/O addressing

 Port-based I/O (parallel I/O)

 Processor has one or more N-bit ports
 Processor’s software reads and writes a port just like a

register
Example: P0 = 0xFF; var = P1.2; P0 and P1 are 8-bit ports
 Bus-based I/O
 Processor has address, data and control ports that form a
single bus
 Communication protocol is built into the processor
 A single instruction carries out the read or write protocol
on the bus
 Hence Address Decoder is required to set port addresses
of peripherals on the bus

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 38

 Compromises/extensions

 Parallel I/O peripheral Processor Memory

 When processor only supports bus- System bus

based I/O but parallel I/O needed Parallel I/O peripheral

 Each port on peripheral connected to a

register within peripheral that is Port A Port B Port C

read/written by the processor Adding parallel I/O to a bus-

based I/O processor
 Extended parallel I/O
Processor Port 0
 When processor supports port-based I/O Port 1
Port 2
but more ports needed Port 3

 One or more processor ports interface

Parallel I/O peripheral

with parallel I/O peripheral extending

total number of ports available for I/O Port A Port B Port C
e.g., extending 4 ports to 6 ports Extended parallel I/O

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 39

 Types of bus-based I/O:
memory-mapped I/O and standard I/O

 Memory-mapped I/O
 Bus has 16-bit address
 lower 32K addresses may correspond to memory
 upper 32k addresses may correspond to peripherals
 Standard I/O (mapped I/O)
 Additional pin (M/IO) on bus indicates whether a memory or
peripheral access
e.g., Bus has 16-bit address
 all 64K addresses correspond to memory when M/IO set to 0
 all 64K addresses correspond to peripherals when M/IO set to 1

08/23/21 Embedded Systems Spring 2010 Shab Ahmed 40

 Memory-mapped I/O vs. Standard I/O
 Memory-mapped I/O
 Requires no special instructions

 Assembly instructions involving memory like MOV work

with peripherals as well

 Standard I/O
 No loss of memory addresses to peripherals

 Simpler address decoding logic in peripherals possible

 When number of peripherals much smaller than address

space then high-order address bits can be ignored

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 41

 A basic memory protocol 8051 Microcontroller

 Interfacing an 8051 to external memory

 Ports P0 and P2 support port-based I/O when 8051 internal

memory being used

 Those ports serve as data/address buses when external

memory is being used

 16-bit address and 8-bit data are time multiplexed; low 8-bits

of address must therefore be latched with aid of ALE signal

 Microprocessor interfacing: interrupts

 When a peripheral receives data, which must be serviced by the

processor
 The processor can poll the peripheral regularly to see if data

has arrived – wasteful

 The peripheral can interrupt the processor when it has data

 Requires an extra pin or pins: Like Int in Intel 8088

 If Int is 1, processor suspends current program, jumps to an

Interrupt Service Routine, or ISR

 Known as interrupt-driven I/O

 Essentially, “polling” of the interrupt pin is built-into the

hardware, so no extra time!

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 43

 Microprocessor interfacing: interrupts

 What is the address (interrupt address vector) of the ISR

(Interrupt Service Routine)?
 Fixed interrupt

 Address built into microprocessor, cannot be changed

 Either ISR stored at address or a jump to actual ISR

stored if not enough bytes available

 Vectored interrupt

 Peripheral must provide the address

 Common when microprocessor has multiple peripherals

connected by a system bus

 Compromise: interrupt address table

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 44

 Interrupt address table
 Compromise between fixed and vectored interrupts
 One interrupt pin

 Table in memory holding ISR addresses (maybe 256 words)

 Peripheral doesn’t provide ISR address, but rather index into

table
 Fewer bits are sent by the peripheral

 Can move ISR location without changing peripheral

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 45

 Additional interrupt issues
 Maskable vs. non-maskable interrupts
 Maskable: programmer can set bit that causes processor to

ignore interrupt
 Important when in the middle of time-critical code
 Non-maskable: a separate interrupt pin that can’t be masked
 Typically reserved for drastic situations, like power failure requiring
immediate backup of data to non-volatile memory
 Jump to ISR
 Some microprocessors treat jump same as call of any subroutine

 Advantage:
Complete state saved (PC, registers) – may take hundreds


of cycles
 Others only save partial state, like PC only
 Thus, ISR must not modify registers, or else must save them first
 Assembly-language programmer must be aware of which registers
stored

08/23/21 Embedded Systems Spring 2010 Shaftab Ahmed 46

 Operating Systems
Instructor: Engr. Muhammad Musa

Lecture # 4 Microprocessor based systems

Introduction to Operating Systems
Chapter #1 Silberschatz

08/23/21 47
 Chapter 1: Introduction

We will discuss the following issues in today’s lecture

 What Operating Systems Do
 Computer-System Architecture
 Operating-System Structure
 Operating-System Operations
 Process Management

 Memory Management

 Storage Management

 Protection and Security

 Distributed Systems
 Special-Purpose Systems
 Computing Environments

08/23/21 48
 What is an Operating System?

 Operating System is a software that executes functions.

It acts as an intermediate b/w a user and the computer
hardware.
 Operating system goals:

 Execute user programs and solve in easier way.

 Make the computer system convenient to use.

 Use the computer hardware in an efficient manner.

08/23/21 49
 Computer System Structure
 Computer system can be divided into four components
 Hardware

 CPU, memory, I/O devices etc.

 Operating system

 Controls hardware among various applications and

users.
 Application programs The way how system programs

are used to solve problems of the users.

 Word processors, compilers, web browsers, database

systems, video games

 Users

 People, machines, other computers

08/23/21 50
 Four Components of a Computer System

08/23/21 51
 Computer Startup

 Bootstrap program is loaded and computer starts and

initialize all aspects of system
 Information stored in ROM or EPROM, generally known
as firmware
 Loads operating system kernel and starts execution
 Program Development Cycle
 Compiling
 Linking
 Loading
 Executing / Debugging

08/23/21 52
 Computer System Organization
 Computer-system operation
 One or more CPUs, device controllers connect through

common bus providing access to shared memory

 Concurrent execution of CPUs and devices competing for

memory cycles

08/23/21 53
 Computer-System Operation

 I/O devices and the CPU can execute concurrently.

 Each device controller is in charge of a particular
device type.
 Each device controller has a local buffer.
 CPU moves data from/to main memory to/from local
buffers
 I/O is from the device to local buffer of controller.
 Device controller informs CPU that it has finished its
operation by causing an interrupt.

08/23/21 54
 Common Functions of Interrupts

 Interrupt transfers control to the interrupt service

routine through the interrupt vector, which contains
the addresses of all the service routines.
 Interrupt architecture must save the address of the
interrupted instruction.
 Incoming interrupts are disabled while another
interrupt is being processed to prevent a lost interrupt.
 A trap is a software-generated interrupt caused either
by an error or a user request.
 An operating system is interrupt driven.

08/23/21 55
 Interrupt Handling

 The operating system preserves the state of the CPU

by storing registers and the program counter.
 Determines which type of interrupt has occurred:
 polling

 interrupt vector system

 Separate segments of code determine what action

should be taken for each type of interrupt

08/23/21 56
 I/O Structure
 Option # 1 Synchronous
when I/O starts, control returns to user program only upon
I/O completion.
 Wait instruction idles the CPU until the next interrupt
 At most one I/O request is outstanding at a time, no
simultaneous I/O processing.
 Option # 2 Asynchronous
After I/O starts, control returns to user program without
waiting for I/O completion.
 System call – allow user to wait for I/O completion.
 Device-status table contains entry for each I/O device
indicating its type, address, and state.
 Operating system indexes into I/O device table to determine
device status and to modify table entry to include interrupt.

08/23/21 57
 Two I/O Methods

Synchronous Asynchronous

08/23/21 58
 Device-Status Table

08/23/21 59
 Direct Memory Access Structure

 Used for high-speed I/O devices to transmit

information at close to memory speeds.
 Device controller transfers data from buffer to main
memory without CPU intervention.
 Only one interrupt is generated per block, rather than
one interrupt per byte.

08/23/21 60
 Storage Structure

 Main memory – it is large storage media that the CPU

can access directly.
 Secondary storage – extension of main memory that
provides large nonvolatile storage capacity.
 Magnetic disks – rigid metal or glass platters covered
with magnetic recording material
 Disk surface is logically divided into tracks, which

are subdivided into sectors.

 The disk controller determines the logical

interaction between the device and the computer.

08/23/21 61
 Storage Hierarchy

 Storage systems organized in hierarchy.

 Speed

 Cost

 Volatility

 Caching – copying information into faster storage

system; main memory can be viewed as a last cache
for secondary storage.

08/23/21 62
 Storage-Device Hierarchy

Size
Speed
Cost
Accessibi
lity
Volatility

08/23/21 63
 Caching

 Cache is faster storage space in the storage hierarchy

 First the cache is checked for data / program
if found it is a hit otherwise a miss
On cache miss the data is read from RAM and copied
to the cache for future use
 Cache is smaller than storage being cached
 Cache management is an important design decision
 Cache size and replacement policy has to be implemented
 Cache does not only apply to CPU and Memory but to
other levels of storage hierarchy also

08/23/21 64
 Operating System Types

 Single user System

It cannot keep CPU and I/O devices busy at all times
 Multiprogramming
 Multiprogramming organizes jobs for a number of users so
that the CPU always has one to execute
 Timesharing (multitasking)
It is logical extension in which CPU switches between a
user’s Processes and interactive computing

08/23/21 65
 Requirements

 Response time should be < 1 second

 Each user has at least one process executing in memory
 If several processes are ready to run at the same time
CPU scheduling is required
 If processes don’t fit in memory, swapping moves them
in and out to run
 Virtual memory allows execution of processes not
completely in memory

08/23/21 66
 Operating-System Operations
Operations Required are:
 Interrupt driven by hardware / software
 Software service request creates exception or trap e.g.
 Opening a file is a service request

 Processes requests the Kernel to access the operating

system area in memory

 Error reporting e.g. division by zero

 Dual-mode operation allows OS to protect itself and other system

components from users
 The two modes are, User mode and kernel mode

 Mode bit is provided by hardware

 It provides ability to distinguish when system is running

user code or kernel code

 Privileged instructions execute in kernel mode only

 System call changes mode to kernel, return from call

resets it to user mode

08/23/21 67
 Dual mode operation by OS

08/23/21 68
 Role of Timers in Operating System
 Timers are used to prevent infinite periods. it is set to interrupt
the OS after specific period
 Operating system decrements counter

 When counter zero generate an interrupt to the device or

process concerned
 Set up before scheduling process to regain control or

terminate program that exceeds allotted time

08/23/21 69
 Process Management
 A process is a program in execution. It is a unit of work within the
system.
 Program is a passive entity, process is an active entity.
 Process needs resources to accomplish its task
 CPU, memory, I/O, files

 Initialization data

 Process termination requires reclaim of any reusable resources

 Single-threaded process has one program counter specifying
location of next instruction to execute
 Process executes instructions sequentially, one at a time, until

completion
 Multi-threaded process has one program counter per thread
 Typically system has many processes running concurrently on one
or more CPUs
 Concurrency is achieved by multiplexing the CPUs among the
processes / threads
08/23/21 70
 Process Management Activities

 Preemption vs Collaboration
 The operating system is responsible for the following
activities in connection with process management:
 Creating and deleting both user and system processes
 Suspending and resuming processes
 Providing mechanisms for process synchronization
 Providing mechanisms for process communication
 Providing mechanisms for deadlock handling

08/23/21 71
 Memory Management
 Data is in memory before and after processing
 All instructions in memory in order to execute
 Memory management determines what is in memory when
 Optimizing CPU utilization and computer response to

users
 Memory management activities
 Keeping track of which parts of memory are currently

being used and by whom

 Deciding which processes (or parts thereof) and data to

move into and out of memory

 Allocating and deallocating memory space as needed

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 Storage Management
 OS provides uniform, logical view of information storage
 Abstracts physical properties to logical storage unit - file

 Each medium is controlled by device (i.e., disk drive, tape drive)

 Varying properties include access speed, capacity, data-

transfer rate, access method (sequential or random)

 File-System management
 Files usually organized into directories

 Access control on most systems to determine who can access

what
 OS activities include

 Creating and deleting files and directories

 Primitives to manipulate files and dirs

 Mapping files onto secondary storage

 Backup files onto stable (non-volatile) storage media

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 Mass-Storage Management
 Usually disks used to store data that does not fit in main memory
or data that must be kept for a “long” period of time.
 Proper management is of central importance
 Entire speed of computer operation hinges on disk subsystem
and its algorithms
 OS activities
 Free-space management

 Storage allocation

 Disk scheduling

 Some storage need not be fast for example:

 Optical storage, Floppy Disk, Magnetic tape

 Varies between WORM (write-once, read-many-times) and RW

(read-write)

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 I/O Subsystem

I/O subsystem responsible for

 Memory management of I/O i.e. Buffering, Caching, Spooling
 General device-driver interface
 Drivers for specific hardware devices

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 Protection and Security
 Protection – Mechanism for controlled access of OS resources by
processes or users
 Security – Defense of the system against internal and external
attacks
 Authentication
 Systems generally first distinguish among users, to determine

allowed activities and access to resources by assigning

 User identities i.e. Name and associated number (X,XXX]
 Group identifier allows set of users to be defined and managed
collectively
 UID is used to provide access control detail
 Privilege escalation allows user to change to effective ID with
more rights
 User ID then associated with all files, processes of that user to
determine access control

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 Computing Environments

Computing environments facilitate user interaction in a

convenient and controlled manner, some of them are:
 Desktop environment
 Network or client server environment
 Peer to Peer computing environment
 Web based cluster / grid environment
 Distributed Operating Systems
 Real Time Operating systems
 Parallel Operating systems
 Ubiquitous Systems

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