Verification of Vlsi Circuits Using Systemverilog: Vinay Reddy

Verification of VLSI Circuits using
SystemVerilog
Vinay Reddy
Department of Electronics & Communication Engineering
1
VERIFICATION OF VLSI CIRCUITS USING
SYSTEMVERILOG
Verilog Stratified Event Queue
Vinay Reddy
Department of Electronics and Communication Engineering
2
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
4 Regions
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SYSTEMVERILOG
Races within the RTL code
Vinay Reddy
28
29
30
It is a Synchronous Circuit
All flops will sample at the same

time since it’s a synchronous clk (It
not a serial circuit, its real
concurrent)
31
It is a Synchronous Circuit
All flops will sample at the same

time since it’s a synchronous clk (It
not a serial circuit, its real
concurrent)
In reality we have clk to q delay

which helps us to maintain the
setup and hold times.
32
Note:
When the clk and data are changing at the

same time, clk is supposed to sample the
old value.
33
Verilog Styles
Dataflow
Behavioural
Structural
34
For simplicity, lets restrict our

discussion to first two always
blocks
35
Verilog Stratified Event Queue Case 1
Assume second always block
executes first
36
Execution of first always block
37
Reading and writing has happened

on the same variable q1 at the same
time in the same region.
Simulation output matches with the

hardware output.
No issues here
38
Verilog Stratified Event Queue Case 2
Assume first always block
executes first
39
Execution of second always

block
40
Reading and writing has happened

on the same variable q1 at the same
time in the same region.
Simulation output does not match

with the hardware output.
Issue Exists - Problem
41
Verilog Stratified Event Queue Solution
42
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG Proof for slide no 26,
Verilog Stratified Event Queue Guideline 1
NBA helps to see the old value

of the flop while sampling
43
SYSTEMVERILOG
What is RTL ?
Vinay Reddy
44
What is RTL ?
45
Is the above circuit RTL ?
46
Successful Communication (Rule : We both have agreed once he talks I will listen
and once I talk he will listen, ie, this is our synchronization)
Karthik : Hi sir, Can I talk to you for some time if u are free now? (Generating the
data, writing the data out (Input to vinay and output from karthik))
Vinay : Hi Karthik, yeah… (sampling the data/Listening while Karthik is talking

(Input), while replying I have to generate the data (output))
Karthik : ……………………….
Vinay : ………………………..
47
Here the logic levels are transferred

through Flops.
The inputs and outputs will be sampled

at some clock frequency and now this
circuit is synchronous.
In reality all the codes are RTL
48
49
Device 1 & Device 2

communicates in
cycle level.
Device 1
Device 2
50
Device 1 & Device 2

communicates in cycle level.
Hence we have to send the

signals to device 2 mimicking
the device 1 (Testbench
Stimulus)
Hence while driving the

stimulus we use it @posedge
clk (Since everything happens
Device 1 in cycle level)
Device 2
51
SYSTEMVERILOG
Races between RTL & Testbench
Vinay Reddy
52
Verilog Stratified Event Queue RTL Code
53
54
55
56
57
58
59
Verilog Stratified Event Queue Race between testbench and RTL
60
How do we overcome the race ?
61
Hence it is compulsory to
use non blocking operator
while generating stimulus
and driving method. (Race
between the testbench
module and the Design
Module)
In reality there will be

number of blocks waiting on
the posedge clk both on the
TB and DUT. To make
verification engineers task
esay SV has come up with the
Program Block
62
Thread 1
Thread 2
Thread 3
63
SYSTEMVERILOG
How do we overcome the races between

the RTL & TB?
Vinay Reddy
64
Verilog Stratified Event Queue and how to overcome the race ?
65
SYSTEMVERILOG
SystemVerilog Stratified Event Queue
Vinay Reddy
66
SV Stratified Event Queue
67
The program blocks are executed

far away from the NBA Region ie,
Reactive region of SV
68
The program blocks are executed

far away from the NBA Region ie,
Reactive region of SV
69
70
SYSTEMVERILOG
Program Block
Vinay Reddy
71
Program Block
72
Program Block
73
Program Block
74
Program Block
75
Program Block
76
Program Block
77
Program Block
Bunch of signals connecting PB O/Ps to RTL I/Ps
78
Program Block This is how a Top module
looks in verification industry
Module top generates the clk and connects the PB and RTL Top Module
Clk is I/P to PB and RTL 79

Program Block
Generation of stimulus
80
Program Block
81
Program Block
82
Program Block
PB can only be instantiated in the module 83

Program Block
Students to read it --
84
SYSTEMVERILOG
A Verilog Memory Model – Self Checking

TB
Vinay Reddy
85
Verilog Memory Model – Question
86
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG Solution : RTL Block
Verilog Memory Model – Architectural Level (Block Diagram)
87
Verilog Memory Model – Behavioural Level (RTL Code)
reg [31:0] mem [16]
88
Verilog Memory Model – Behavioural Level (RTL Code)
89
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG Solution : Self Checking TB Block
Verilog Memory Model – Behavioural Level (TB Code)
90
DUT Instantiation
All the task methods are called inside the initial block
91
Task : Reset
92
Task : Write data (Stimulus Generation / Driving the DUT)
93
Task : Read data (Collecting the outputs from DUT and storing it in got_arr)
94
Task : Compare (Comparing the written data and the read data)
95
Task : Results (Displaying the Results)
96
SYSTEMVERILOG
A Verilog Memory Model TB – TB using PB
Vinay Reddy
97
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG Solution : TB Using PB
TOP Module
98
Program Block
PB Declarations
99
Program Block Read task
Initial block
Compare task
Reset task
Result task
Write task
100
Verilog Memory Model – Behavioural Level (TB Code) In reality, the number of ports
on a system will be huge
TOP Module
What happens if we
miss match the port
connections ?
Do we get any
compile error ?
101
Verilog Memory Model – Behavioural Level (TB Code) In reality, the number of ports
on a system will be huge
TOP Module
What happens if we
miss match the port
connections ?
Do we get any
compile error ?
We don’t get compile

error but functionality
will be effected.
This debugging leads to

waste of time and does
not anyways add value
to the design.
102
SYSTEMVERILOG
Interfaces
Vinay Reddy
103
Interface
Top Module
104
Interface
105
Interface
106
Interface
107
SYSTEMVERILOG
Modports
Vinay Reddy
108
Modports
109
Modports
110
Modports
111
Modports
112
Modports
113
SYSTEMVERILOG
BUS Arbiter Communication Example – without

interface and with interface
Vinay Reddy
114
Arbiter Communication
rst req[0] req[1] gr[0] gr[1]

1 x x 0 0
0 0 1 0 1
0 1 0 1 0
According to
DUT 0 1 1 the priority
115
Arbiter Communication Arbiter RTL Code
Request [1:0] = req[0] – Device 1 (printer),

req[1] – Device 2 (Memory)
116
Arbiter Communication Arbiter TB Code
It waits for two clock cycles
117
Arbiter Communication Arbiter Top module Code
118
Arbiter Communication Example
119
Arbiter Communication with Interfaces
120
121
122
123
124
125
126
127
128
SYSTEMVERILOG
Clocking Blocks
Vinay Reddy
129
Clocking Blocks
• All chips communicate at cycle level

• Hence we have to generate stimulus at cycle level
• All SOCs have multiple clocks
• Synchronization Issues is resolved with clocking blocks
• Clocking Blocks are not Synthesizable
• We have to assemble the signals w.r.t their paticular clocks
130
Clocking Blocks
131
Clocking Blocks
Clocking Block
Asynchronous reset
132
Clocking Blocks
Outputs in TB can be
driven and inputs in TB
can be sampled 133
Clocking Blocks
Interface Module
Program Block
Adding clocking block to the interface block
Top Module RTL Module
134
Clocking Blocks
135
Clocking Blocks
4
3
2
136
Clocking Blocks
At Time 0
• Total 5 Concurrent blocks
- Always block in top module

- 3 Always blocks in DUT
- $Display in Program block
137
Clocking Blocks
At Time 0
It is blocked for 5 time units
All these concurrent blocks are also pending/waiting

138
Clocking Blocks
At Time 0
It is blocked for 5 time units
All these concurrent blocks are also pending/waiting

139
Clocking Blocks
140
Clocking Blocks
141
Clocking Blocks
142
Clocking Blocks
At time 5
It samples the new Value
X - 10
143
Clocking Blocks
Data = 1 reaches the RTL at #2 but

in reality the communication
takes place in Cycle Level not in
individual time levels.
144
Clocking Blocks
145
Clocking Blocks
1 at #2
X at #2
146
Clocking Blocks
Old New
1 at #2 RTL samples the old value
X - 1 at #5
not the new value
147
Clocking Blocks
148
Clocking Blocks
Driving stimulus
Sampling
149
Clocking Blocks
Questions to ask yourself

1. At what simulation Time are we
in ?
2. Is there a clk edge available at
this point ?
3. When is the next posedge of the
clk?
150
Clocking Blocks
Note: Clocking block executes in the

Re-NBA Region

in ?
this point ?
clk?
151
Clocking Blocks

Re-NBA Region
152
Clocking Blocks

Re-NBA Region
153
Clocking Blocks
154
Clocking Blocks
#2
T0
1. 0, X,X,X
T1
T2
Outp1 = x
T5
10,20 155
Clocking Blocks
#6
10,20 156
Clocking Blocks
#5
10,20 157
Clocking Blocks
158
Clocking Blocks
Lets go to T5 Slot directly
1, X
Outp1 = 0
159
Clocking Blocks
Lets go to T5 Slot directly
#1 step
Questions to ask yourself
in ?
this point ?
1, X clk?
Outp1 = 0
160
Clocking Blocks
161
Clocking Blocks
162
Clocking Blocks
163
Clocking Blocks
164
Clocking Blocks Students HW
165
166
THANK YOU
Vinay Reddy
Department of Electronics & Communication Engineering
vinay@pes.edu
+91 9945730244
167

Verification of Vlsi Circuits Using Systemverilog: Vinay Reddy

Uploaded by

Copyright:

Available Formats

You might also like

Verification of Vlsi Circuits Using Systemverilog: Vinay Reddy

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Verification of Vlsi Circuits Using Systemverilog: Vinay Reddy

Uploaded by

Copyright:

Available Formats

Verification of VLSI Circuits using

Verilog Stratified Event Queue

Races within the RTL code

All flops will sample at the same

All flops will sample at the same

In reality we have clk to q delay

When the clk and data are changing at the

For simplicity, lets restrict our

Execution of first always block

Reading and writing has happened

Simulation output matches with the

Execution of second always

Reading and writing has happened

Simulation output does not match

Issue Exists - Problem

NBA helps to see the old value

Is the above circuit RTL ?

Vinay : Hi Karthik, yeah… (sampling the data/Listening while Karthik is talking

Here the logic levels are transferred

The inputs and outputs will be sampled

In reality all the codes are RTL

Device 1 & Device 2

Device 1 & Device 2

Hence we have to send the

Hence while driving the

Races between RTL & Testbench

How do we overcome the race ?

In reality there will be

How do we overcome the races between

SystemVerilog Stratified Event Queue

The program blocks are executed

The program blocks are executed

Bunch of signals connecting PB O/Ps to RTL I/Ps

Clk is I/P to PB and RTL 79

PB can only be instantiated in the module 83

A Verilog Memory Model – Self Checking

reg [31:0] mem [16]

Task : Write data (Stimulus Generation / Driving the DUT)

Task : Results (Displaying the Results)

A Verilog Memory Model TB – TB using PB

We don’t get compile

This debugging leads to

BUS Arbiter Communication Example – without

rst req[0] req[1] gr[0] gr[1]

Request [1:0] = req[0] – Device 1 (printer),

It waits for two clock cycles

• All chips communicate at cycle level

Adding clocking block to the interface block

Top Module RTL Module

- Always block in top module

All these concurrent blocks are also pending/waiting

All these concurrent blocks are also pending/waiting

Data = 1 reaches the RTL at #2 but

Questions to ask yourself

Note: Clocking block executes in the

1. At what simulation Time are we

Note: Clocking block executes in the