Agile implementation of a

fully parameterizable funnel

shifter
- Bhawandeep Singh
 Requirements/ Interfaces
➢ An RTL module with
○ input data of width in_word_size
○ output data of width
out_word_size
○ in_word_size and out_word_size
Funnel Shifter
may or may not have any
relationship. in_word_size bit out_word_size
input bit output
➢ Real systems can also involve clock Decoupled Decoupled
crossing, not addressed here, does not
impact the funnel shifter part, since
funnel shifter becomes active after Input word 0 Input word 1
clock crossing is already finished.
O/p 2 Partial
O/P 0 O/P 1 O/P 3
O/P 4
 Applications

➢ x86 based CPU with variable length instructions

➢ ASICs that may have similar requirements, incoming data and

outgoing data may be of different widths, with the wider side
not necessarily a multiple of the narrower side
 Design
out
Decoupled
In out_word_size
Flipped (
manager_state_machine
Decoupled) empty
in_word_size
push empty
pull
wp B
Sync FIFO rp
U
F
F
E
Data R
(in_word_size)
 Specification + Constraints
➢ Input and output side data widths are different, constant and parameterizable
(in_word_size and out_word_size) with no relationship required between them. Even
prime values like 31 and 17 work.
➢ Any side may be wider.
➢ No clock crossing.
➢ Writing side FIFO size is parameterizable (mem_size) for any expected burst sizes.
➢ Buffer size is parameterizable (buffer_size).
➢ Funnel shifter full when Sync FIFO is full, empty when BUFFER is empty. Design
ensures that if FIFO is not full and BUFFER has sufficient space, data is pulled
automatically into BUFFER.
 Verification/ Results
Test 1 - test_funnel_shifter_empty
➢ Initially, empty must be asserted and full deasserted.
➢ After 1st write, for writing width wider than reading width, empty must stay asserted for
1CC more till data is moved from FIFO to BUFFER. Then empty must be deasserted.

Test 2 - test_funnel_shifter_full
➢ When FIFO gets full, it must be correctly detected and full output of funnel_shifter must be
asserted.
➢ Fifo should not get full, if there is space in the buffer for a complete entry.
➢ Buffer full must be detected correctly and asserted.
 Verification/ Results
Test 3 - test_funnel_shifter_1
➢ Funnel shifter must deassert empty correctly once data is available.
➢ Circular buffer manager for FIFO memory must work correctly at wraparound for both
write pointer as well as read pointer
➢ If FIFO is not empty, and either there is enough space in buffer to store one word from
FIFO, or there will be enough space after the active pull, then pull must be asserted to FIFO
to bring a word from FIFO into buffer, to effectively save 1CC.
 Verification/ Results
Test 4 - test_funnel_shifter_0
➢ Funnel shifter must return bit/ range selections of written data correctly on every pull
➢ Funnel shifter must be able to concatenate ranges from different written words correctly at
crossover of written words
➢ Funnel shifter must be able to concatenate ranges from different written words correctly at
buffer wraparound.
➢ When all data has been read, funnel shifter must finally assert empty with data_out = 0.
 Verification/ Results

Test 5 - test_funnel_shifter_input_narrower
➢ Funnel shifter must keep bringing written words from memory into buffer but must empty
asserted till enough data is available to be read in a single read word.
➢ Empty must also stay asserted while buffer has less data than reading word size
➢ Funnel shifter must join written words and return a read word correctly.
 Incremental development

➢ Phase 1 - Synchronous FIFO implementation and testing

➢ Phase 2 - Funnel shifter design, implementation and basic testing
➢ Phase 3 - Corner case testing and enhancement to save 1CC.
➢ Phase 4 - Updated push-pull interface to Decoupled interface.
 Documentation

The github documentation details the following -

➢ The module description - what it does etc.
➢ Link to uploaded slides with design diagram and test cases.
➢ The repo contents and the directory structure
➢ The steps to run the tests.
 Learnings

➢ For me, this was one digital module I did not have a clear idea how to do it, now I do.
➢ The design was the major learning and most of them are generic and transferable -
○ It’s easier if memory word size matches the writing width rather than the reading width
○ It is easier to store words read from memory into a buffer and then select bits than to
do it any other way.
○ buffer be a vector of bits rather than a memory or a vector of words.
○ In summary, a buffer of bits should be present at the boundary of bit width conversion
and there should be a memory before it to handle any mismatches in clock frequencies
or burst sizes.
➢ The project seems easier after having done it.
➢ A few of my doubts in Chisel syntax that had persisted, were cleared during the project
especially related to order of statements/ assignments to Reg.
➢ Now I also have ideas on what enhancements can be tried.
 Future enhancements
➢ Clock crossing can be added to the present design/ implementation. This will just need
replacing of the synchronous fifo with an asynchronous fifo at the front end.

➢ An interesting and now seemingly doable project is to have either of in_word_size or

out_word_size or even both as variable rather than constant. They can be made ports rather
than parameters and instantaneous value can be used for each write and read. Handling full
and empty instantaneously for a cycle based on instantaneous in_word_size and
out_word_size, respectively, will be interesting. By logical extension, any size that is
different from memory width, it’s interface will need a buffer in the form of vector of bits.
 Future enhancements
➢ The present design only sends one word per clock cycle from FIFO to Buffer even if FIFO
Has more words available and Buffer can take more words. THis causes more clock cycles
if in_word_size << out_word_size even though data may be transferred in 1CC. The width
of this transfer may be increased with num_requested being communicated from
Funnel_shifter_manger to FIFO and num_returned communicated from FIFO to Funnel
shifter manager and BUffer update.
➢ If the FIFO is empty, and buffer has partial data or not, when new data comes, it still passes
through the FIFO. This may be bypassed in cases where there is no CDC and data may be
either directly stored in Buffer or if enough data is available, then sent out directly without
losing clock cycles.
Questions