DSP Design Flows in Fpga: © 2003 Xilinx, Inc. All Rights Reserved

DSP Design Flows
in FPGA
© 2003 Xilinx, Inc. All Rights Reserved

Objectives
After completing this module, you will be able to:
• Describe the advantages and disadvantages of three different design flows
• Use HDL, CORE Generator, or System Generator for DSP depending
on design requirements and familiarity with the tools
• Explain why there is a need for an integrated flow from system design
to implementation
• Describe the System Generator and the tools it interfaces with
• Build a model, simulate it, generate VHDL, and go through the design flow
• Describe how Hardware in the Loop verification is beneficial in complex
system design
DSP Design Flows in FPGA - 2 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Using HDL
• Using the Xilinx CORE
Generator
• Using the Xilinx System
Generator for DSP
• HDL Co-Simulation
• Hardware Verification
• In System Debug
• Resource Estimator
• Summary
• Simulink Tips and Tricks
HDL Design Verification
Implement your
Behavioral design using VHDL
HDL Simulation
or Verilog
Functional
Synthesis Simulation
Timing
Implementation Simulation
In-Circuit
Download Verification
Synthesis Design Verification
Behavioral
HDL Simulation
Synthesize the
Functional
Synthesis Simulation design to create an
FPGA netlist
Timing
In-Circuit
Implementation
Design Verification
Behavioral
HDL Simulation
Functional
Translate, place
Implementation Timing and route, and
Simulation
generate a
bitstream to
In-Circuit download in the
Download Verification FPGA
Labs 1-3: Generating a MAC
• You will be generating the MAC using three different methods
– Using VHDL
– Using the Xilinx CORE Generator
– Using the Xilinx System Generator for DSP
• Compare the implementation results
• Contrast the design methodologies
Lab 1
Create a MAC using VHDL:
• Become familiar with the VHDL design flow, which includes:
– Writing a small piece of VHDL code
– VHDL simulation with ModelSim VHDL
– Synthesizing a design using Xilinx XST
– Implementation using the Xilinx ISE tools
• Create a 12 x 8 MAC by writing the behavioral code for a multiplier and
accumulator
• Note: For non-VHDL users, a solution is provided in the lab1_soln

directory
Block Diagram: VHDL MAC
A A mult_in
1 t Q
2 2 2
B
0 7
8 Multiplier rdy_in Accumulator
t
ND
CLR
CLK
Wrap up
• Implementation results: 66 Slices, ~130 MHz
• Important to notice:
– Global clock buffer is automatically instantiated
– Embedded multiplier is used by default in Virtex™-IIP devices. In this lab,
the option was turned off in order to use slice-based multipliers
• Timing constraint should always be used to achieve the performance
required
– UCF file must be generated manually
• Remember size to compare with the other flows
Outline
• Using HDL
Generator
Generator for DSP
• Summary
CORE Generator
Design Verification
HDL
Instantiate optimized
Behavioral IP within the HDL
Simulation
COREGen code
Functional
Timing
In-Circuit
Synthesize, Implement, Download
Design Verification
HDL Behavioral
Simulation
COREGen
Functional
Synthesize,
Implement, and
Timing Download the
Implementation Simulation bitstream,
similar to the
original design
In-Circuit flow
Xilinx IP Solutions
DSP
DSP Functions
Functions Math
Math Functions
Functions Memory
Memory Functions
Functions
$P Additive White Gaussian Noise (AWGN) P Multiplier Generator P Asynchronous FIFO

$P Reed Solomon - Parallel Multiplier P Block Memory modules
$ 3GPP Turbo Code - Dyn Constant Coefficient Mult P Distributed Memory
$P Viterbi Decoder - Serial Sequential Multiplier P Distributed Mem Enhance
P Convolution Encoder - Multiplier Enhancements P Sync FIFO (SRL16)
$P Interleaver/De-interleaver P Pipelined Divider P Sync FIFO (Block RAM)
P LFSR P CORDIC P CAM (SRL16)
P 1D DCT P CAM (Block RAM)
P 2D DCT Base
Base Functions
Functions
P DA FIR
P MAC P Binary Decoder
P MAC-based FIR filter P Twos Complement
Fixed FFTs 16, 64, 256, 1024 points P Shift Register RAM/FF
P FFT 16- to 16384- points P Gate modules
P FFT - 32 Point P Multiplexer functions
P Sine Cosine Look-Up Tables P Registers, FF & latch based
P Adder/Subtractor IP CENTER
$P Turbo Product Code (TPC)
P Direct Digital Synthesizer P Accumulator
P Cascaded Integrator Comb P Comparator http://www.xilinx.com/ipcenter
P Bit Correlator P Binary Counter
P Digital Down Converter
Key: $ = License Fee, P = Parameterized, S = Project License Available,
BOLD = Available in the Xilinx Blockset for the System Generator for DSP
Xilinx CORE Generator
List of available IP from

or
Fully
Parameterizable
Xilinx Smart-IP Technology
• Pre-defined placement and routing enhances performance and predictability
Fixed Fixed Placement &
Relative Placement Placement Pre-defined
I/Os Routing
Other logic has Guarantees I/O Guarantees

no and Performanc
effect on the core Logic Predictability e
• Performance is independent of:
200 200
MHz MHz
Core Placement
Number of Cores
Device Size
200
200 MHz
MHz
Outputs
• .EDN (EDIF implementation netlist)
• .XCO (core implementation data file / log file)
• Optional:
– .ASY Foundation or Innoveda symbols
– .VEO Verilog instantiation template
– .V Verilog behavioral simulation model
– .VHO VHDL instantiation template
– .VHD VHDL behavioral simulation model
Lab 2
Creating a MAC using Core Generator
• Become familiar with the CORE Generator design flow, which includes:
– Generating CORE Generator macros
– Instantiating the macros in VHDL
– Simulating VHDL with CORE Generator macros in ModelSim
– Synthesizing a design using Xilinx XST
– Implementation using the Xilinx ISE 6 tools
• Create a 12 x 8 MAC by generating a multiply accumulator using the
CORE Generator
Wrap up
• Implementation results: 71 slices, 175 MHz
• Important to notice:
– Global clock buffer should be instantiated because the synthesis tool may
not know which signal is the clock because it is looking at a black box
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
The Challenges for a
DSP Software Platform
• Industry Trends
– Trend towards platform chips (FPGAs, DSP) resulting in greater complexity
– Highly flexible systems required to meet changing standards
– Multiple design methodologies - control plane/datapath
– Challenges in modeling and implementing an entire platform
– Hardware in the loop verification is useful in complex system design and System
Generator supports it
• System Design Challenges
– Leveraging legacy HDL code
– Modeling & implementing control logic and datapath
– No expert exists for all facets of system design
MATLAB
• MATLAB™, the most popular system design tool, is a programming
language, interpreter, and modeling environment
– Extensive libraries for math functions, signal processing, DSP,
communications, and much more
– Visualization: large array of functions to plot and visualize your data and
system/design
– Open architecture: software model based on base system and domain-
specific plug-ins
MATLAB
• Frequency response of
input sound file
Simulink
• Simulink™ - Visual data flow environment for modeling and simulation of
dynamical systems
– Fully integrated with the MATLAB engine
– Graphical block editor
– Event-driven simulator
– Models parallelism
– Extensive library of parameterizable functions
• Simulink Blockset - math, sinks, sources
• DSP Blockset - filters, transforms, etc.
• Communications Blockset - modulation, DPCM, etc.
MATLAB/Simulink
Real time frequency response from a
microphone: emphasizes the dynamic nature
of Simulink
Traditional Simulink
FPGA Flow
System Architect System Verification
GAP Simulink
FPGA Designer
HDL
Synthesis Functional Simulation Verify Equivalence
Implementatio Timing Simulation

n
Downloa In-Circuit Verification

d
System Generator for
DSP v6.2 – An Overview
• Industry’s system-level design environment (IDE) for FPGAs
– Integrated design flow from Simulink to bit file
– Leverages existing technologies
• Matlab/Simulink R13.1 or R14 from The MathWorks
• HDL synthesis
• IP Core libraries
• FPGA implementation tools
• Simulink library of arithmetic, logic operators and DSP functions (Xilinx
Blockset)
– Bit and cycle true to FPGA implementation
• Arithmetic abstraction
– Arbitrary precision fixed-point, including quantization and overflow
– Simulation of double precision as well as fixed point
System Generator for
DSP v6.2 – An Overview
VHDL code generation for Virtex-II Pro™, Virtex™-II, Virtex™-E,
Virtex™, Spartan™-3, Spartan™-IIE and Spartan™-II devices
– Hardware expansion and mapping
– Synthesizable VHDL with model hierarchy preserved
– Mixed language support for Verilog
– Automatic invocation of CORE Generator to utilize IP cores
– ISE project generation to simplify the design flow
– HDL testbench and test vector generation
– Constraint file (.xcf), simulation ‘.do’ files generation
– HDL Co-Simulation via HDL C-Simulation
• Verification acceleration using Hardware in the Loop
Mathworks R14 Compliant!
• System level modeling tool
– Release 13.1 or R14
• Xilinx implementation tools - ISE 6.2i
• Synthesis
– XST & Project Navigator within ISE 6.2i
– Leonardo Spectrum LS 2003b.35
– Synplify v7.2
• HDL Simulation
– ModelSim 5.7e
System Generator for DSP
Platform Designs
PCI/JTAG
System Generator Based
Design Flow
MATLAB/Simulink
HDL
System Generator System Verification
Synthesis Functional Simulation
Implementation Timing Simulation
Download In-Circuit Verification
Design Flow
MATLAB/Simulink Files Used
HDL •Configuration file
System Generator System Verification •VHDL
•IP
•Constraints File

HDL-CoSimulation
Design Flow
MATLAB/Simulink Files Used
HDL •Configuration file
System Generator System Verification •VHDL
•IP
•Constraints File
HWIL-CoSimulation
Creating a System
Generator Design
• Invoke Simulink library browser
• To open the Simulink library browser,
click the Simulink library browser
button
or type “Simulink” in MATLAB console
• The library browser contains all the
blocks available to designers
• Start a new design by clicking the
new sheet button
Creating a System
Generator Design
• Build the design by dragging and dropping blocks
from the Xilinx blockset onto your new sheet.
• Design Entry is similar to a schematic editor
Connect up blocks by pulling
the arrows on the sides of
each block
Finding Blocks
• Use the Find feature to search ALL
Simulink libraries
• Xilinx blockset has nine major sections
– Basic elements
• Counters, delays
– Communication
• Error correction blocks
– Control Logic
• MCode, Black Box
– Data Types
• Convert, Slice
– DSP
• FDATool, FFT, FIR
– Index
• All Xilinx blocks – quick way to view all blocks
– Math
• Multiply, accumulate, inverter
– Memory
• Dual Port RAM, Single Port RAM
– Tools
• ModelSim, Resource Estimator
Configure Your Blocks
• Double-click or go to Block Parameters
to view a block’s configurable parameters
– Arithmetic Type: Unsigned or twos complement
– Implement with Xilinx Smart-IP Core (if possible)/
Generate Core
– Latency: Specify the delay through the block
– Overflow and Quantization: Users can saturate or
wrap overflow. Truncate or Round Quantization
– Override with Doubles: Simulation only
– Precision: Full or the user can define the number
of bits and where the decimal point is for the block
– Sample Period: Can be inherent with a “-1” or
must be an integer value
• Note: While all parameters can be simulated,
not all are realizable
Values Can Be Equations
• You can also enter equations in the
block parameters, which can aid
calculation and your own understanding
of the model parameters
• The equations are calculated at the
beginning of a simulation
• Useful MATLAB operators
– + add
– - subtract
– * multiply
– / divide
– ^ power
– π pi (3.1415926535897.…)
– exp(x) exponential (ex)
Important Concept 1:
The Numbers Game
• Simulink uses a “double” to represent numbers in a simulation. A double is a “64-bit twos
complement floating point number”
– Because the binary point can move, a double can represent any number between +/- 9.223 x
1018 with a resolution of 1.08 x 10-19 …a wide desirable range, but not efficient or realistic for
FPGAs
• Xilinx Blockset uses n-bit fixed point number (twos complement optional)
-22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 Value = -2.261108…
1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1
Format = Fix_16_13
Integer Fraction (Sign: Fix = Signed Value
Format = Sign_Width_Decimal point from the LSB UFix = Unsigned value)
Design Hint: Always try to maximize the dynamic range of design by using only the required number of bits
Thus, a conversion is required when communicating with Xilinx blocks with Simulink blocks (Xilinx
blockset → MATLAB I/O → Gateway In/Out)
What About All Those
Other Bits?
• The Gateway In and Out blocks support parameters to control the
conversion from double precision to N - bit fixed point precision
DOUBLE
-26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13
.... 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 ....
OVERFLOW
QUANTIZATION
- Wrap
- Saturate - Truncate
- Flag Error - Round
-22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9
1 0 1 1 0 1 1 1 1 0 1 0
FIX_12_9
Other Type: Boolean
• The Xilinx Blockset also uses the
type Boolean for control ports like
CE and RESET
• The Boolean type is a variant on

the 1-bit unsigned number in that
it will always be defined (High or
Low). A 1-bit unsigned number
can become invalid; a Boolean
type cannot
Fractional Number Formats
Using the technique shown, convert the following fractional values…
• Define the format of the following twos complement binary fraction and calculate
the value it represents
Format = < _ _ >
1 1 0 0 0 1 1 0 1 0 1 1
Value =
• What format should be used to represent a signal that has:

a) Max value: +1 b) Max value: 0.8 c) Max value: 278
Min value: -1 Min value: 0.2 Min value: -138
Quantized to 12 bit Quantized to 10 bit Quantized to 11 bit
data data data
Format = < _ _ > Format = < _ _ > Format = < _ _ >
• Fill in the table:
Creating a System
Generator Design
I/O blocks used as interface between the Xilinx
Blockset and other Simulink blocks
Simulink sources SysGen blocks realizable Simulink sinks and

in Hardware library functions
Sample Period
• Every SysGen signal must be “sampled”; transitions occur at equidistant
discrete points in time called sample times
• Each block in a Simulink design has a “Sample Period” and it
corresponds to how often that block’s function is calculated and the
results outputted
• This sample period must be set explicitly for:
• Gateway in
• Blocks w/o inputs (note: constants are idiosyncratic)
• Sample period can be “derived” from input sample times for other blocks
Sample Period
• The units of the sample period can be thought of as arbitrary, BUT a lot
of Simulink source blocks do have an essence of time
– For example, a sample period of 1/44100 means the block’s function will be
executed every 1/44100 of a sec
• Remember Nyquist Theorem (Fs ≥ 2fmax) when setting sample periods
• The sample period of a block DIRECTLY relates to how that block will be
clocked in the actual hardware. More on this later
Setting the Global
Sample Period
• The Simulink System Period
MUST be set in the System
Generator token. For single
rate systems it will be the
same as the Sample Periods
set in the design. More on
Multi Rate designs later
Sample Period = 1
SysGen Token
Master Slave
Controls Controls
“Simulink System
Period” MUST be set
correctly for
simulation to work
Using the Scope
• Click Properties to change the number of
axes displayed and the time range value
(X-axis)
• Use the Data History tab to control how
many values are stored and displayed
on the scope
– Also can direct output to workspace
• Click Autoscale to quickly let the tools
configure the display to the correct axis
values
• Right-click on the Y-axis to set its value
Design and Simulate
in Simulink
Push “play” to simulate the design. Go to “Simulation
Parameters” under the “Simulation” menu to control the
length of simulations
Generate the VHDL Code
Once complete, double-click
the System Generator token
• Select the target device

• Select to generate the testbench
• Set the System clock period desired
• Generate the VHDL
System Generator
Output Files
• Design files
– .VHD : VHDL design files
– .EDN : Core implementation file
– .XCF : Xilinx constraints file for timing constraints
• Project files
– .NPL : Project Navigator project file
– .TCL : Scripts for Synplify and Leonardo project creation
• Simulation files
– .DO : Simulation scripts for MTI
– .DAT : Data files containing the test vectors from System Generator
– .VHD : Simulation testbench
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
HDL Co-simulation
Allows Import of HDL Code
• Being able to include new or legacy modules is essential for many DSP system
designers
• HDL modules can be imported into Simulink
– “Black box” function allows designers to import HDL
– Single HDL simulator for multiple black boxes
– HDL modules can be simulated in Simulink to significantly reduce development time
• HDL is co-simulated transparently
– HDL simulated using industry-standard ModelSim tool from Mentor Graphics directly
from Simulink framework
Import HDL code
Drag a Black
Box
into the model
Configuration
Wizard
detects VHDL
files &
customizes block
Co-Simulate with ModelSim
Select
ModelSim
Drag a ModelSim Simulink Simulation
block into the opens Mode
model ModelSim
and
co-simulates
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
Hardware-in-the-Loop Reduces
Design Time & Cost
• Configure any development board for hardware-in-the-loop using JTAG
header in <20 minutes
– Automatically create FPGA bit-stream from Simulink
– Transparent use of FPGA implementation tools
– Accelerate and verify the Simulink design using
FPGA hardware
– Mirrors traditional DSP processor design flows
• Combine with black box to simulate HDL & EDIF
Create Bit-stream
Step
Step11
Select
Select
Target
Target
H/W
H/W
Platform
Platform
Step 2
Generate
Generate
Bit-stream
Bit-stream
Co-Simulate in Hardware
Step
Step 33 contd.
contd.
Post-generation
Post-generation
script
script creates
creates aa
new
new library
library
containing
containing aa
parameterized
parameterized
run-time
run-time co-
co-
simulation
simulation block.
block.
Step
Step 55
Simulate
Simulate for
for
verification
verification
Step
Step 44
Copy
Copy the
the aa co-
co-
simulation
simulation run-
run-
time
time block
block into
into the
the
original
original model.
model.
Hardware in the Loop
Performance Results
Single Step Clock Mode (bit and cycle
accurate) Software Hardwar
Applicatio Simulatio e
Speed-
n Simulatio
n up
Time n
Image (seconds)
67 Time
6 112
Filtering 6 (seconds)
X
QAM Demodulator + 120 1 67
Extension 3 8 X
5 x 5 Image 17 4 43
Filter 0 X
Cordic Arc 18 2 7
Tangent 7 7 X
Additive White Gaussian Noise 60 8 7.5
Channel 0 0 X
Free Running Clock
Mode
A free running clock is provided to the design, thus the hardware is no longer running in
lockstep with
the software. The test is started, and after some time a 'done' flag is set to read the results
from the
FPGA and display them in Simulink. Using this hardware co-simulation method, designers
can achieve
up Flows
DSP Design to 6 inorders of- 60magnitude performance
FPGA - 2 enhancement over original
© 2003 Xilinx, Inc. All Rights Reserved
software
For Academic Usesimulation.
Only
Choice of Target Hardware
• Hardware-in-the-loop development platforms:
– Xilinx
• XtremeDSP Development kit
• Multimedia Board
– Distributors:
• Avnet, Insight, Nu Horizons
– Key board vendors
• Alphadata, Annapolis, Nallatech, Lyrtech…
– You?
• Configure your JTAG-based board in 20 minutes
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
In-System Debug at Near
System Speeds
• Insert Chipscope block
into Simulink design
• Configure FPGA using
JTAG interface
• Perform in-system debug
at near system speeds
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
Resource Estimator
• The block provides fast estimates of
FPGA resources required to
implement the subsystem
• Most of the blocks in the System
Generator Blockset carries the
resources information
– LUTs
– FFs
– BRAM
– Embedded multipliers
– 3-state buffers
– I/Os
Resource Estimator
• Three types of estimation
– Estimate Area
• This option computes
resources for the current level
and all sub-levels
– Quick Sum
• Uses the resources stored in
block directly and sum them
up (no sub-levels functions
are invoked)
– Post-Map Area
• Opens up a file browser and
let user select map report file.
The design should have been
generated and gone through
synthesis, translate, and
mapping phases.
Lab 3
Build a MAC with System Generator:
• Goals: Gain familiarity with the SysGen v6.1 and its design flow,
including ProjNav, synthesis tools (XST), ModelSim simulators, and the
ISE implementation tools. Use Resource Estimator to estimate
resources used by the design. Familiarize with hardware in the Loop flow
• Background: The multiply-accumulate (MAC) operation is fundamental in
digital signal processing and numerous other applications
a
+ c
b
c = Σi aibi N-
For example, the output of a digital filter with impulse response h i 1
and input sequence xi, is given by:
yn = i=
Σ xn-i hi
0
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
Summary
• Full VHDL/Verilog (RTL code)
– Advantages:
• Portability
• Complete control of the design implementation and tradeoffs
• Easier to debug and understand a code that you own
– Disadvantages:
• Can be time-consuming
• Don’t always have control over the Synthesis tool
• Need to be familiar with the algorithm and how to write it
• Must be conversant with the synthesis tools to obtain optimized design
Summary
• Full VHDL/Verilog (Instantiating Primitives)
– Advantages:
• Full access to all architecture features
• Carry on further with optimization
• Best optimization
– Disadvantages:
• Not as portable as RTL VHDL/Verilog
• Must be an FPGA expert and know the architecture
• Time-consuming
Summary
• CORE Generator
– Advantages
• Can quickly access and generate existing functions
• No need to reinvent the wheel and re-design a block if it meets specifications
• IP is optimized for the specified architecture
– Disadvantages
• IP doesn’t always do exactly what you are looking for
• Need to understand signals and parameters and match them to your
specification
• Dealing with black box and have little information on how the function is
implemented
Summary
• System Generator for DSP
– Advantages
• Huge productivity gains through high-level modeling
• Ability to simulate the complete designs at a system level
• Very attractive for FPGA novices
• Excellent capabilities for designing complex testbenches
• HDL Testbench, test vector and golden data written automatically
• Hardware in the loop simulation improves productivity and provides quick verification of
the system functioning correctly or not
– Disadvantages
• Minor cost of abstraction: doesn’t always give the best result from an area usage point of
view
• Customer may not be familiar with Simulink
• Not well suited to multiple clock designs
• No bi-directional bus supported
Outline
• Using HDL
Generator
Generator for DSP
• In System Debug
• Summary
Simulink Tips and Tricks
• Throughout this course, we will disperse various tips and tricks that we
find useful when using Simulink to create System Generator designs
Complete Systems
• Throughout this course,
we will build and study small
sections of complete systems
• To get a flavor of the capability
of System Generator,
check out the demos
• Type “demos” from
the MATLAB command line
to view them
Combining Signals
• To be viewed on a scope, multiple
signals must first be combined
• Use the MUX block (Simulink library
→ Signals & Systems) to combine signals, thus making
a vector out of them
• Check Format → Signal Dimensions
and Format → Wide NonScalar Lines
to view how many signals are combined Type ‘vector’
• Similarly, the DEMUX can be used to to view the example
separate signals
Creating Subsystems
• All large designs will utilize hierarchy
• Select the blocks to go into the
subsystem. Click and drag to
highlight a design region
• Select “Create Subsystem” in
the Edit Menu
– Ctrl+G has the same effect
• Use the modelbrowser under
the “View” menu to navigate
the hierarchy
• Hierarchy in the VHDL code
generated is determined by subsystems
Documenting a Design
• Double-click the background to create
a textbox
• Type in the text
• Right-click the text to change format

• Left-click to move the textbox around
• A masked subsystem can be given
“Help” documentation. More on this
later
Inports and Outports
• Allow the transfer of signal
values between a subsystem
and a parent
• Inport and Outport block

names are reflected on the
subsystem
• Can be found in Simulink

→ Sinks (for the Outport)
and Simulink → Sources
(for the Inport)
Inputting Data
from the Workspace
• “From Workspace” block can
be used to input MATLAB data
to a Simulink model Type ‘FromWorkspace’
to view the example
• Format:
– t = 0:time_step:final_time;
– x = func(t);
– make these into a matrix
for Simulink
• Example:
– In the MATLAB console,
type: t = 0:0.01:1;
x = sin(2*pi*t);
simin = [t', x'];
Outputting Data
to the Workspace
• “To Workspace” block can be used to
output a signal to the MATLAB
workspace
• The output is written to the workspace
Type ‘ToWorkspace’ when the simulation has finished or is
to view the example paused
• Data can be saved as a structure
(including time) or as an array

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DSP Design Flows

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• Note: For non-VHDL users, a solution is provided in the lab1_soln

$P Additive White Gaussian Noise (AWGN) P Multiplier Generator P Asynchronous FIFO

List of available IP from

Other logic has Guarantees I/O Guarantees

Synthesis Functional Simulation Verify Equivalence

Implementatio Timing Simulation

Downloa In-Circuit Verification

Synthesis Functional Simulation

Implementation Timing Simulation

Download In-Circuit Verification

Implementation Timing Simulation

Download In-Circuit Verification

Implementation Timing Simulation

Download In-Circuit Verification

• The Boolean type is a variant on

• What format should be used to represent a signal that has:

Simulink sources SysGen blocks realizable Simulink sinks and

• Select the target device

• Right-click the text to change format

• Inport and Outport block

• Can be found in Simulink

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