Chip Architecture and Power Density

Integration of diverse functionality on

SoC causes major variations in activity
(and hence power density)

Today: steep
gradients

The past: temperature

uniformity
Temperature variations cause
performance degradation –
higher temperature means
slower clock speed
09/10/2021 1
 Temperature Gradients (and Performance)
Copper hat (heat sink on top not shown)

SiC spreader (chip underneath spreader)

Glass ceramic substrate

IBM Power PC 4 temperature map

Hot spot:
138 W/cm2
(3.6 x chip avg flux)

09/10/2021 2
09/10/2021 3
 Power The Dominant Design Constraint (3)
Exciting emerging applications require “zero-power”
Example: Computation/Communication Nodes
for Wireless Sensor Networks

Meso-scale
Meso-scalelow-cost
low-costwireless
wirelesstransceivers
transceiversfor
for
ubiquitous
ubiquitouswireless
wirelessdata
dataacquisition
acquisitionthat
that
•• are
arefully
fullyintegrated
integrated
–– Size
Sizesmaller
smallerthan
than11cm
3
cm3
•• are
aredirt
dirtcheap
cheap
–– At
Atororbelow
below1$ 1$
•• minimize
minimizepower/energy
power/energydissipation
dissipation
–– Limiting power dissipation to 100 mW
Limiting power dissipation to 100 mW
enables
enablesenergy
energyscavenging
scavenging
•• and
andform
formself-configuring,
self-configuring,robust,
robust,ad-hoc
ad-hocnetworks
networks
containing
containing100’s
100’stoto1000’s
1000’sofofnodes
nodes

09/10/2021 4
 How to Make Electronics Truly Disappear?

From 10’s of cm3 and 10’s to 100’s of mW

To 10’s of mm3 and 10’s of mW