VLSI System Design Methodology: Unit 1

UNIT 1
VLSI System Design Methodology

Design of VLSI Systems: Unit 1 Sujay S N, Assistant Professor, Dept. of ECE, Dr. AIT
Design Methodology:
Hierarchy
•“divide and conquer”

• dividing a system into modules
Regularity
•the designer attempts to divide the hierarchy into a set of similar
building blocks.
•At the circuit level, uniformly sized transistors can be used,
•while at the gate level, a finite library of fixed-height, variable-
length logic gates can be used.
•At the logic level, parameterized RAMs and ROMs could be used
in multiple places.
•At the architectural level, multiple identical processors can be
used to boost performance.
Modularity
•Modularity states that modules have well-defined functions and

interfaces.
•If modules are “well-formed,” the interaction with other modules can
be well characterized.
Locality
•By defining well-characterized interfaces for a module, we are
effectively stating that other than the specified external interfaces, the
internals of the module are unimportant to other modules.
•In this way we are performing a form of “information hiding” that
reduces the
•apparent complexity of the module.
Top-down Design Methodology
 Define the top-level block and identify the sub-blocks
necessary to build the top-level block.
Further subdivide the sub-blocks until we come to leaf
cells, which are the cells that cannot further be divided.
Bottom-up Design Methodology
First identify the building blocks that are available to us.
We build bigger cells, using these building blocks.
These cells are then used for higher-level blocks until we
build the top-level block in the design.
Design Methods:
Microprocessor/DSP
Many times, the most practical method to solve a system design

problem is to use a standard microprocessor or digital signal processor
(DSP).
There are many single-chip microprocessors with built-in RAM and
EEROM/EPROM available in the market.
Microprocessors provide great flexibility because systems can be
upgraded in the field through software patches.
Programmable Logic
• The cost, speed, or power dissipation of a microprocessor may not meet
system goals and an alternative solution is required.
•A variety of programmable chips are available that can be more efficient
than general purpose microprocessors yet faster to develop than dedicated
chips:
 Chips with programmable logic arrays
 Chips with programmable interconnect
 Chips with reprogrammable logic and interconnect
The system designer should be familiar with these options for two reasons:
1. It allows the designer to competently assess a particular system
requirement for an IC and recommend a solution.
given the system complexity, the speed of operation, cost goals, time-to-
market goals, and any other top-level concerns.
2. It familiarizes the IC designer with methods of making any chip
reprogrammable at the hardware level and hence both more useful and
more widely applicable.

Programmable Logic Devices: programmable logic arrays (PLAs)
A PLA consists of an AND plane and an OR plane to

compute any function expressed as a sum of products.
Each transistor in the AND and OR plane must be
capable of being programmed to be present or not.
This can be achieved by fully populating the AND and OR
plane with a NOR structure at each PLA location.
Each node is programmed with a floating-gate transistor,
a fusible link, or a RAM-controlled transistor, as
illustrated in Figure.
Field-Programmable Gate Arrays (FPGAs)
FPGAs are completely programmable even after a product is shipped

or “in the field.”
Two basic versions exist.

• The first uses a special process option such as a fuse or antifuse
to permanently program interconnect and personalize logic.
• These are one-time programmable.
• The second type uses static RAM or flash memory to configure
routing and logic functions.
First Type:
A special one-time programmable contact, called an antifuse, is placed at
the intersection of routing traces.
These normally have high resistance (effectively an open circuit). Upon
application of a special programming voltage across the contact, the
resistance permanently drops to a few ohms.
CMOS switches allow the programming voltage to be directed to any
antifuse in the chip.
The advantage of this type of routing is that the size of the programmable
interconnect is tiny––the intersection area of two metal traces. Moreover,
the on-resistance is low compared to a CMOS switch, so the circuit speed
is not compromised.
The disadvantage is that the interconnect is not reprogrammable, so once
a chip is programmed, its function is fixed to the extent that the
interconnect has been personalized.
A simple SRAM-based FPGA logic cell is shown in Figure 14.16. It is composed of a
16 × 1 static RAM as the logic element.
•FPGA CLBs configured for a specific Application by
loading configuration data into Internal Static memory
cells.
•Data stored in memory cell determines the functionality
of CLBs, IOBs and routing cells.
•FPGA can read data from external serial PROM in Master
Serial mode.
•Computer can write the data into Slave serial mode.
Gate Array and Sea of Gates Design
•Designers typically strive to keep the non-recurring
engineering cost low as possible.
•One method of doing this is to construct a common base
array of transistors and personalize the chip by altering the
metallization (metal and via masks) that is placed on top of
the transistors.
•This style of chip is called a Gate Array (GA).
•A particular subclass of a gate array is known as a Sea-
of-Gates (SOG) chip.
•Rows of nMOS and pMOS transistors are arrayed in the SOG
portion of the chip.
•Grounding the gate of the nMOS transistor or connecting
the gate of the pMOS transistor to the VDD rail provides
isolation between gates.
SOG cell layout Gate Array cell layouts
Figure 14.17(c) shows a portion of an SOG structure programmed to be a 3-input
NAND gate.
Cell-Based Design
•Cell-based design uses a standard cell library as the basic
building blocks of a chip.
•The cells are placed in appropriate positions, then their
interconnections are routed.
•Cell-based design can deliver smaller, faster, and lower-
power chips than FPGAs but has high NRE costs to
produce the custom mask set.
•Therefore, it is only economical for high volume parts.
•As compared to full custom design, cell-based design
offers much higher productivity because it uses
predesigned cells with layouts.
•Foundries and library vendors supply cells with a wide
range of functionality.
•These include the following:
Small-scale integration (SSI) logic (NAND, NOR, XOR, AOI,
OAI, inverters, buffers, registers)
• Memories (RAM, ROM, CAM, register files)
• System level modules such as processors, protocol
processors, serial interfaces, and bus interfaces Possibility of
mixed-signal and RF modules.
•Whereas Medium Scale Integration (MSI) functions such as

adders, multipliers, and parity blocks used to be supplied as
cells, synthesis engines commonly construct these from base-
level Small Scale Integration (SSI) gates in current design
systems.
•A 1x (normal power) cell commonly is defined to use the widest transistors
that fit within the vertical pitch of the standard cell.
•2x and larger (high power) cells use wider transistors to deliver more
current.
•A single row of nMOS transistors
adjacent to GND (ground) and a single
row of pMOS transistors adjacent to
VDD (power) are normally used.
•The polysilicon gate is connected from

nMOS transistor to pMOS transistor and,
in the case of multiplexers and registers,
the polysilicon connection has to be
crossed between vertically coincident
nMOS and pMOS transistors.
Full Custom Design
•The oldest and most traditional technique is termed
custom mask layout, in which a designer sits in front of a
graphics display running an interactive editor and pieces
designs together at the geometry level one rectangle at a
time.
•This work is sometimes called polygon pushing.
•A variation of custom mask design is called symbolic
layout.
• In these times of cell-based design, digital CMOS ICs use
custom mask design only for the highest of volume parts
such as microprocessor datapaths.
•However, analog and RF designs, cell libraries, memories,
and I/O cells still frequently use custom design.
•From time to time, we have mentioned software generators
as a method of generating physical layout.
•This kind of idea has been around for a long time and was
often referred to as silicon compilation.
Complete microprocessors were typical of layouts that were
generated.
•A “correct by construction” method was used to build the

layouts hierarchically.
• Modern versions of the venerable “silicon compiler” can be

built in a structured hierarchical manner to generate
memories, register files, and other special-purpose
structures that can benefit from a customized layout.
Platform-Based Design––System on a Chip
•As systems have become more complex, the use of predefined
intellectual property (IP) blocks has become commonplace.
•IP: reusable unit of logic or functionality or cell or a layout
design that is normally developed wit the idea of licensing to
multiple vendor for using as building blocks in different chip
designs.
•A platform can be used to implement a design by using
common structures such as busses and common high-level
languages (such as C) to program the processors.
•Platform-based systems typically consist of a basic RISC
processor, which can be extended with multipliers, floating
point units, or specialized DSP units.
• Manual techniques for hardware-software codesign mirror
this approach.
Chip Design Methods
Behavioral synthesis
•Behavioral level : Operation of the system is captured

• without having to specify the implementation
• Eg: Pipelining required may not be specified.
•Best used to debug the operation of the complete system
•Technology independent
For synthesis of complex signal processing architectures:
Cathedral series of silicon compilers
•Cathedral I: which concentrated on bit serial digital filters
•Cathedral II : which complied collections of communicating sequential DSP
processors
•Cathedral III: which aims to video signal processing architectures.
•LAGER : compiler for signal processing architectures.
(These Targeted systems called as silicon compilers because they take design from
behavioral level to mask level)
Behavioral compiler must perform following operations.
• Decide upon and assign resources based on area and timing requirements.
• Insert pipelining registers to achieve timing constraints.
• Create microcode and/or control logic.
RTL synthesis
• Here Commonly RTL description captured using HDL.

• Takes RTL description into set of registers and combinational logic.
• Yorktown silicon compiler system (first approch)
• RTL HDLs have to capture the following attributes of the design.
o Control flow using if-then-else and case statements

o Iteration
o Hierarchy
o Word widths, bit vectors and bit fields
o Sequential versus parallel operations
o Register specification and allocation
o Arithmetic, logic and comparison operations
• Logic optimization is then used to improve the logic to meet timing or
area constraints
•Eg. VHDL code for difference engine
•Signal statement defines some internal signals
•Process statement indicates the section of code to implement
sequentially
•Wait statement indicate the presence of clocked registers
•Case and if operator indicates a multiplexer
•+ operator indicates addition
•< operator indicates a comparison
When combined with a appropriate substrate it may be compiled to

a set of logic gates and registers
Logic optimization
• Takes logic descriptions as generated by an RTL synthesis.
• The registers are reunited with a optimized logic.
• Logic synthesis commenced with logic description

• Form of Boolean equations or a schematic netlist of logic gates
• The objective is to manipulate the logic to meet speed or area constraints or
a combination of both goals
• Logic optimization systems divide the problem into two stages
• A Technology independent phase in which logic is optimized according to
algebraic and/or Boolean techniques
• A Technology mapping phase, which translates the optimized descriptions
into specific library standard cells, FPGA elements, or other implementable
logic gates.
• A Technology independent phase uses a large body of algorithms that
operate on logic networks, using both Boolean and arithmetic techniques.
• Typical flow trough optimization is as follows
• Network organization
• Two-level minimization
• Algebraic decomposition
• Iterative improvement
•First step, to eliminate constant nodes and redundant inverters or
converting the logic to a two level PLA sum of products form.
•Next two level minimization might be invoked.
•‘Expresso’ is an example widely used two level minimization program.
•Next, algebraic decomposition used to introduce new nodes into the
logic network in a manner that minimizes cost.
•One technique known as ‘weak division’ this uses two level logic
expression into multiple level logic expressions.
•Dividing the expressions into sub expressions.
•The most suitable sub expression is chosen by evaluating the cost
function that may be based on reducing the number of literals (area) or
other functions related to the levels of logic (speed).
f1 = aef + bef + ceg
f2 = aeg + bg + def
•Common sub expressions are ef, ae,eg
•ef saves more literals(area)
•When ef is divided into all sub expressions,
f1 = (a+b) t1 + ceg
f2 = aeg + bg + dt1
t1 = ef
Then eg might be chosen, yielding
f1 = (a+b) t1 + ct2
f2= a t2 + bg + dt1
t1 = ef
t2 = eg
 Finally algorithms are used to iteratively improve the logic structure
 this may employ algebraic techniques of extraction, factoring, and
substitution in addition to decomposition.
Following the technology independent step, a technology mapper is
used to optimize the gates for particular technology.
 Rule Based technology mapping.
 Direct- Acyclic-Graph(DAG) converting
• here base function set is chosen
•Eg: two input nand gate and inverter.
•All target library are then described as base function.
Structural – to – layout synthesis
Placement: placing the modules adjacent to each other to minimize

the area or cycle time.
Two main automated algorithms
1. min-cut algorithm
2. Thermal annealing based
1. min-cut algorithm:
• It takes the toplevel of the chip or module and finds two subblocks
with minimum number of signal interconnections.
• two blocks are placed in top and bottom half of the conceptual final
layout.
• this process is repeated for those two halves, split in to quarters.
and so on until the leaf cell are reached.
2. Thermal annealing based
•Modules are allowed to move randomly and the temperature is evaluated

by applying some measure such as routing area or timing.
•As the layout cools, the routing and/or timing improves.
•For each subblock movement, the resulting temperature is calculated.
Routing
•Takes a module placement and a list of connections and connects
modules with wires.
• types of routers: Channel routers, Switch box routers, Maze routers.
•Channel routers route rectangular channels.

•Switch box router routes much complex channel shapes then channel
routers.
•Maze routers can route just about any configuration but have
comparatively long running times. Reserved for really tough routing
problems.
•A global router is a special router that works during a placement
algorithm to try to plan where routers will travel when the layout is
finally placed.
Layout synthesis
•The layout of regular structures such as RAMs, ROMs, PLAs,

Register files, Multiplexers and general data paths may be synthesized
by software generators.
•Takes number of parameters as input and automatically create a

custom physical layout.
•Some systems create actual mask layouts wrt particular

technology,
•Others create symbolic layouts that may be compacted to suit a

particular technology.

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UNIT 1

VLSI System Design Methodology

•“divide and conquer”

•Modularity states that modules have well-defined functions and

Many times, the most practical method to solve a system design

more widely applicable.

A PLA consists of an AND plane and an OR plane to

FPGAs are completely programmable even after a product is shipped

Two basic versions exist.

•Whereas Medium Scale Integration (MSI) functions such as

•The polysilicon gate is connected from

•A “correct by construction” method was used to build the

• Modern versions of the venerable “silicon compiler” can be

•Behavioral level : Operation of the system is captured

Behavioral compiler must perform following operations.

• Here Commonly RTL description captured using HDL.

• RTL HDLs have to capture the following attributes of the design.

o Control flow using if-then-else and case statements

When combined with a appropriate substrate it may be compiled to

• Logic synthesis commenced with logic description

Placement: placing the modules adjacent to each other to minimize

•Modules are allowed to move randomly and the temperature is evaluated

•Channel routers route rectangular channels.

•The layout of regular structures such as RAMs, ROMs, PLAs,

•Takes number of parameters as input and automatically create a

•Some systems create actual mask layouts wrt particular

•Others create symbolic layouts that may be compacted to suit a

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