Module -1:

Module -1:
Fundamentals Of Computer Architecture ( 9 Hours)
Organization of the von Neumann machine; Instruction formats; Pipeline -
fetch/execute cycle, instruction decoding and execution; Registers and register
files; Instruction types and addressing modes; Subroutine call and return
mechanisms; Other design issues.

Prepared by Dr.I. Mala Serene, SITE,VIT University

Registers
 Memory Hierarchy
 Registers
 Cache memory
 Main memory
 Secondary memory
 At higher levels of hierarchy, memory is faster, smaller
and more expensive.
 Number and function vary between processor designs -
one of the major design decisions
 Register-Top level of memory hierarchy
 Two roles
 User-visible registers – referenced by machine instruction
 Control and status registers – employed to control the operation

Prepared by Dr.I. Mala Serene, SITE,VIT University

 User-Visible Registers
• General Purpose
• Data
• Address
• Condition Codes

Prepared by Dr.I. Mala Serene, SITE,VIT University

User Visible Registers
 True general purpose registers – register can contain the
operand for any Opcode
 Restricted – used for specific operations – floating point
and stack operations. (dedicated registers)
 Data registers – used only to hold data and cannot be
employed in the calculation of an operand address –
Accumulator (AC)
 Address registers – devoted for particular addressing
mode.
 Segment registers – holds the address of the base of the
segment.
 Index registers – used for indexed addressing and may be auto-
indexed
 Stack pointer – points to the top of the stack (if there is a user-
visible stack addressing, stack is in memory)

Prepared by Dr.I. Mala Serene, SITE,VIT University

Design Issues
 Specialized registers
 Implicit in the Opcode, Saves bits (small instructions)
– because of less number of specialized registers,
Less flexibility
 General purpose registers
 Increased instruction size, increased flexibility and
programmer options
 Number of GP, data + address registers: 8 to 32
is optimum
 Fewer registers result in more memory references

Prepared by Dr.I. Mala Serene, SITE,VIT University

How big?

 Large enough to hold full address

 Large enough to hold data of most data types
 But often possible to combine two data registers
or two address registers by using more complex
addressing

Prepared by Dr.I. Mala Serene, SITE,VIT University

Condition Code Registers – Flags
 Condition codes are bits set by the CPU hardware as the
result of operations.
 Machine instructions allow these bits to be read by
implicit reference.
 Programmer cannot alter them
 In some machines, sub-routine call will result in the
automatic saving of all user-visible registers, to be
restored on return.
 Sets of individual bits, flags
 e.g. result of last operation was zero
 Can be read by programs
 e.g. Jump if zero – simplifies branch taking

Prepared by Dr.I. Mala Serene, SITE,VIT University

Control & Status Registers
 Not visible to the user
 May be visible in a control or operating system
mode (supervisory mode)
 Registers essential to instruction execution:
 Program Counter (PC)
 Instruction Register (IR)
 Memory Address Register (MAR) – connects to
address bus
 Memory Buffer Register (MBR) – connects to data
bus, feeds other registers

Prepared by Dr.I. Mala Serene, SITE,VIT University

Program Status Word
 Contains status information+Condition Codes:
 Sign (of last result)
 Zero (last result)
 Carry (multiword arithmetic)
 Equal (two latest results)
 Overflow
 Interrupts enabled/disabled
 Supervisor/user mode

Prepared by Dr.I. Mala Serene, SITE,VIT University

Example Register Organizations

Prepared by Dr.I. Mala Serene, SITE,VIT University

Register Files (RF)
 Set of general purpose registers.
 It functions as small RAM and implemented
using fast RAM technology.
 Register Files needs several access ports for
simultaneously reading from or writing to several
different registers. Hence Register Files is
realized as multiport RAM.
 A standard RAM has just one access port with
an associated address bus and data bus.
 A register file with three access ports - symbol

Data in C
16
2
Address C Port C

Register File
RF
2 2
Address A Port A Port B Address B

16 16
Data out A Data out B

Prepared by Dr.I. Mala Serene, SITE,VIT University

 A Register File with three access ports – logic diagram

1011 Ex: R3 ← R1 + R2
Data in C Read Address A = 01
16 Read Address B = 10
2 4-way 16-bit
Write Address C = 11
Write 11
S demultiplexer
address C

16 16 16 16

16-bit register R3 16-bit

0110register R2 16-bit
0101register R1 16-bit register R0
16 16
●
16 ●
● 16
●

2 4-way 16-bit 4-way 16-bit 2

S S 10
01 multiplexer multiplexer
Read Read
address A 16 16 address B
Data out A
Data out B

Prepared by Dr.I. Mala Serene, SITE,VIT University

Questions
 If the 8 registers are used
 How many bits are needed for read/write address?
 What is the size of the demultiplexer and multiplexer
required?
 How many multiplexers and demultiplexer’s are
required to perform three read and one write
operation?
 If 4 multiplexers are used, how many parallel
reads can be performed?
 If 2 demultiplexers are used, how many parallel
writes can be performed?
 Design a register file that stores eight 32 bit
numbers and has one read and one write port.

Prepared by Dr.I. Mala Serene, SITE,VIT University

References

 W. Stallings, Computer organization and

architecture, Eighth edition [refer page: [453-
458]
 J. P. Hayes, Computer system architecture,
McGraw Hill [refer page : [257-259]