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Vme Bus: Vinay Shet
Vme Bus: Vinay Shet
Vme Bus: Vinay Shet
Vinay Shet
Introduction
• VME - Versa Module Europa
• Flexible, open-ended bus system using the
Eurocard Standard
• Introduced by Motorola, Mostek and Signetics
in 1981
• It was intended to be a flexible environment,
supporting a variety of computing intensive
tasks.
• Defined in IEEE 1014-1987 standard
Introduction
• In 1981, Motorola decided to second source
the MC68000 microprocessor chip
• Motorola proposed the use of VERSA bus
backplane
• However, the others rejected this proposal
saying that the VERSA bus board size was
much too large
• In response, Motorola proposed that they use
the (much smaller) Eurocard board instead
Introduction
• VERSA bus electrical specifications and
Eurocard mechanical specifications
VME bus features
• Master / slave architecture
DTACK
MASTER SLAVE
• Advantages?
VME bus features
• Addressing
• Provides variety of address spaces and data
widths – Dynamic address and data sizing
• Makes no distinction between IO space and
Memory space
• Uses three address spaces
• 16-bit (A16)
• 24-bit (A24)
• 32-bit (A32)
• 6 bit address modifier code is used to distinguish
between these address spaces
VME bus features
• Data Transfer
• Provides variety of data widths – Dynamic data sizing
• Data transfer sizes can be
• 8-bit
• 16-bit
• 32-bit
• Data transfer cycles can be Single Cycle or Block Transfer
• Single Cycle – Address is sent with each data transfer
• Block Transfer – one address is sent with multiple data
transfers
VME bus features
• Data Transfer Cycles
• Single cycles – D8(O), D8(EO), D16, D32 and
MD32
• Block Transfer – BLT, MBLT, A40BLT
• Mixing different address and data widths
• You can use different address and data widths
based on the application
• Common examples
• A16/D8(O) – simple IO boards
• A32/D32 – high performance modules
VME bus features
• Data Transfer Speed
VMEbus
BLT 40 Mbyte/sec
IEEE-1014
320 - 500+
VME320 2eSST
Mbyte/sec
VME bus features
• Byte Ordering
• VME bus does not specify byte ordering
• Most devices use the Motorola model which is big
endian, but the Digital model is little endian
• Two models are provided to accomplish byte
swapping
• VMS bus adapter
• Software interfaces
VME bus features
• Interrupts Vectors
• VME bus interrupt vectors range from 0x00
to 0xFF, inclusive.
• The bus adapter consumes some of these
adapters and area not available to the
device drivers
• Interrupt Priorities
• Seven interrupt priorities (IRQ1 through
IRQ 7 – IRQ7 highest priority)
VME bus features
• Bus Arbitration
• With single master, life is easy – when system
boots, the master asks for the bus, gets it and
keeps it.
• VME provides 4 separate bus request levels
• Two or more masters can request the bus at the
same time on the same request level
• If multiple requests on same level then proximity to
slot one is used to determine who will get the bus
VME bus features
• Bus Arbitration
• E.g M(3) and M(7) request on level 1 at
same time M(3) will get the bus first
• M(7) has to wait until M(3) has finished and
then assuming no one form slot 1 – 6
requests then M(7) gets bus
• Arbitration is done by the System
Controller – always resides in slot 1
VME bus features
• Bus Arbitration
• Arbitration can be set up in
• Priority mode
• Round robin mode
• Single level mode
• Releasing the bus
• RWD – Release when done
• ROR – Release on request (usually
implemented in H/W hence faster)
VME bus features
• Bus Arbitration
• Fairness
• In heavily loaded system, first four boards can
hog the bus and starve the rest.
• To prevent this – bus requesters are
programmed to request bus only when bus
request lines are not asserted – Fairness
• This ensures that all boards – even in a heavily
loaded system – eventually get the bus
VME bus features
• Live insertion capability
• Electronic module can be removed and inserted in
the system when the power is on
• Also known as Hot Swap
• Typical Board de-allocation Process
• System admin software disables new connections to
board’s device driver
• System waits for all connections to terminate or forces
existing connections to terminate
VME bus features
• VMEbus System Controller
• Resides in slot 1
• Bus Arbitration
• Provides 16 MHz system clock (SYSCLK)
• Provides the interrupt acknowledge (IACK) daisy chain
driver
• VMEbus Daisy Chains
• Five daisy chain signals on VME bus – four used for
bus arbitration and one for interrupt acknowledge
• Bus arbitration done using 4 bus request lines and 4
bus grant in/out lines
VME bus features
Architecture Master/slave
Addressing Range 16, 24, 32, 40 or 64-bit Address path width selected dynamically.
Architecture Master/slave
Addressing Range 16, 24, 32, 40 or 64-bit Address path width selected dynamically.
VME bus features
• Summary of features
Data Path Width 8, 16, 24, 32 or 64-bit Data path width selected dynamically.
Live Insertion
Yes Using optional standards.
Capability
Conduction Cooled
Version Yes Under IEEE 1101.2
(Military)