DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING
IMPLEMENTATION OF STFT FOR AUDITORY COMPENSATION ON FPGA
ABSTRACT OBJECTIVES
Literature survey to understand current algorithms in auditory
In this project, properties of Short Time Fourier Transform (STFT) and human auditory system have been exploited to design a novel approach for digital hearing aids. The filter bank
approach which is currently used to design digital hearing aids has two banks of filters- analysis and synthesis filter bank. Owing to the advances in VLSI technology over decades, a compensation.
circuit fast enough could be designed to function as analysis FB, determine the dominant sub-band (for that period) and the required gain for that frequency in real-time and apply the To investigate the STFT algorithm for auditory compensation on
same to the real-time incoming signal, the fact that human ears process sound in quasi-stationary manner could be leveraged to compensate for the circuit delay. Since Discrete Fourier
MATLAB.
Transform can be used as analysis FB, the same can be used, depending on frequency resolution required, the length of DFT can be varied. The Fast Fourier Transform is used instead
of DFT as the divide and conquer approach used in the former significantly reduces number of complex multiplications required, consequently decreasing the circuit complexity and Realize the STFT algorithm for the same in Verilog HDL
thereby increasing the speed of the circuit. Hearing aids are required to determine spectrum of the input signal instantaneously. The local spectrum can be obtained by windowing the FPGA Implementation
input signal over a specific time period. Additionally, “hop length” can be defined between two successive windows as duration for which the input signal is masked from the CONCLUSION
subsequent processing units since the sampling time is generally much shorter than the response time of human auditory system. By masking the inputs, subsequent circuitry is kept
constant, which implies, lesser power will be consumed by the circuit. In this project, alternate frames are processed, the gain value is calculated for nth frame, for the (n+1)th frame, gain Hearing loss is diagnosed when a person is unable to hear
value obtained for nth frame is simply multiplied with the real-time input signal instead of calculating it again, by simulating on Simulink it was ensured that audio quality was not 25 decibels in at least one ear. Treatment depends on the cause and
deteriorated. The Verilog code was written for the whole system and was implemented on Xilinx Artix-7.
severity of hearing loss. The hearing aid is the most commonly used
solution. The STFT approach for auditory compensation was verified
on Simulink and was implemented on Xilinx Vivado w.r.t Artix-7
FPGA. Though filter bank approach provides high quality and high
personalization, its resource utilization is significantly higher. By
merely determining the dominant frequency component for that instant
and applying gain, replaces the reconstruction process followed in FB
approach. Frequency resolution can be changed by varying the FFT
length and window length. STFT introduces a new paradigm for the
design of digital hearing aids and can replace the filter-bank approach.
FUTURE SCOPE
This project emphasizes on signal processing block of the digital
hearing aid, the design and implementation of peripheries of the digital
hearing aid such as ADC and DAC are not taken into consideration.
Custom memory blocks could be designed to hold the gain values in
full-custom style.

Team Members Project Guide

Kajal Awasthi (1NT17EC056), Rajeev B R (1NT17EC112), Vikas M B (1NT17EC171) Dr./Prof. S L Pinjare B-25