Chapter 2

Introduction to Assembly
Chapter 2
The AVR microcontroller

and embedded
systems
using assembly and c
AVR Microcontroller and Embedded System Using © 2011 Pearson Higher Education,
Assembly and C Upper Saddle River, NJ 07458. • All Rights
Topics
 AVR’s CPU
 Its architecture
 Some simple programs
 Data Memory access
 Program memory RAM EEPROM Timers
 RISC architecture PROGRAM

Flash ROM
Program Data
 RISC vs. CISC Bus
CPU
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
AVR’s CPU
 AVR’s CPU
 ALU
 32 General Purpose
R0
registers (R0 to R31) R1
ALU
 PC register R2
…
 Instruction decoder SREG: I T H S V N Z C
R15
CPU R16
R17
…
PC
R30
Instruction decoder
R31
Instruction Register
registers
AVR GPRs and ALU
Some simple instructions
1. Loading values into the general purpose registers
LDI (Load Immediate) – load constant values in a

GPR
 LDI Rd, k (can be decimal, octal, binary, hexa)
 Rd: R16 to R31 only

 Its equivalent in high level languages: R0
ALU R1
Rd = k (8 bits) R2
…
 Example: SREG: I T H S V N Z C
CPU
R15
 LDI R16,53 R16
R17
 R16 = 0x35 = $35 PC
…
 LDI R19,132; R19 = 0x84 Instruction decoder
R30
R31
 LDI R23,0x27; R23 = 0x27 Instruction Register
registers
2. Arithmetic calculation
 There are some instructions for doing Arithmetic
and logic operations; such as:
ADD, SUB, MUL, AND, etc.
 ADD Rd,Rs
 Rd = Rd + Rs R0
ALU R1
 Example: R2
…
 ADD R25, R9 SREG: I T H S V N Z C
CPU
R15
 R25 = R25 + R9 R16
R17
 ADD R17,R30 PC
…
 R17 = R17 + R30 Instruction decoder
R30
R31
registers
A simple program
 Write a program that calculates 19 + 95
LDI R16,19
LDI R17,95
ADD R16,R17
R0
ALU R1
R2
…
SREG: I T H S V N Z C
CPU
R15
R16
R17
PC
…
R30
Instruction decoder
R31
registers
A simple program
 Write a program that calculates 19 + 95 + 5
LDI R16,19
LDI R17,95
ADD R17,R16; R16 = 19 =$13, R17 = 114 = $72
LDI R18,5
ADD R17,R18; R18 = 5, R17 = $77
LDI R16,19
LDI R17,95
LDI R18,5
ADD R17,R16; R16 = 19 =$13, R17 = 114 = $72
ADD R17,R18; R18 = 5, R17 = $77
 SUB Rd,Rs
 Rd = Rd - Rs
 Example:
 SUB R25, R9
 R25 = R25 - R9 R0
ALU R1
 SUB R17,R30 R2
…
 R17 = R17 - R30 SREG: I T H S V N Z C
CPU
R15
R16
R17
PC
…
R30
Instruction decoder
R31
registers
 INC Rd – INCREMENT THE VALUE OF Rd BY 1
 Rd = Rd + 1
 Example:
 INC R25
 R25 = R25 + 1 R0
ALU R1
R2
…
 DEC Rd SREG: I T H S V N Z C
CPU
R15
 Rd = Rd - 1 R16
R17
 Example: PC
…
R30
 DEC R23 Instruction decoder
R31
 R23 = R23 - 1 registers
Address
I/O
$00
Mem.
$20
Name
TWBR
I/O
$16
Data Address Space
Address
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H
$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B
$04 $24 ADCL $1A $3A DDRA $2F $4F TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
$06 $26 ADCSRA $1C $3C EECR OCDR
$07 $27 ADMUX $1D $3D EEDR $31 $51 General RAM EEPROM Timers
OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 Purpose
TCNT0
$09 $29 UBRRL $1F $3F PROGRAM
EEARH $33 $53 Registers
TCCR0
$0A $2A UCSRB UBRRCROM $34 $54 MCUCSR
$20 $40
$0B $2B UCSRA UBRRH $35 $55 MCUCR
Program CPU
$0C $2C UDR $21 $41 WDTCR $36 $56 TWCRData
$0D $2D SPCR $22 $42 ASSR Bus
$37 $57 SPMCRBus address bus
$0E $2E SPSR $23 $43 OCR2 $38 $58 TIFR data bus
control bus
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK Data
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit $46
$26 ICR1L $3B $5B GICR Bus
Data Address
$12 $32 PORTD $27R0 $47 ICR1H $3C $5C OCR0
Space
$13 $33 PINC $28R1 $48 OCR1BL $3D $5D SPL
$14
$0000 $34 DDRC $29R2 $49 OCR1BH $3E $5E SPH Interrupt Other
General
$0001 $35
$15 PORTC OSC Ports
$2A $4A OCR1AL $3E $5E SREG Unit Peripherals
...
Purpose
...
Registers R31
$001F I/O Address I/O
$0020 Example:
TWBR
TWSR
$00 Add contents
$01
of location
Example: 0x90
Store to contents
0x53 into the of location
PINS SPH 0x95
register.
Standard I/O Example:
and store What doesinthe
the result following
location
The
LDS
STS (Load
(Store instruction
0x313.
address of
directSPH do?space)
isdata
from
direct to 0x5E
data space)
Example: Write a program that stores 55 into location 0x80 of RAM.
...
Example: Write a program that copies the contents of location 0x80

...
Registers
Solution:
SPH $3E
$005F
$0060
of LDS
RAM
SREG $3FR20,2
into location 0x81.
LDS
STS Rd, addr ;[addr]=Rd
addr,Rd ;Rd = [addr]
General
LDS R20, 0x90 Solution:
Solution: ;R20 = [0x90]
purpose Answer:
...
RAM
(SRAM) LDS R20,
Solution:
LDI R21, 55 Example:
0x95 LDI R20, 0x53
;R20 =;R21
55 = [0x95]
;R20 = 0x53
It copies
ADD
the contents
R20, R21
of
STSR2 ;R20
into R20;
0x5E,= R20as+ 2R21
R20
is the;SPH
address
= R20of R2.
STS
LDS 0x80, R20 LDS
R20, 0x80 STS R1,
0x60,R15
;[0x80] =0x60
;R20 R20 ; [0x60] = R15
= 55
= [0x80]
STS 0x313, R20 ;[0x313] = R20
$FFFF
STS 0x81, R20 ;[0x81] = R20 = [0x80]
DRAW THE MEMORY MAP FOR THE DATA ADDRESS SPACE
FOR AVR ATMEGA32 WITH 1KB OF RAM
000000000000 = $000 $0000

001111111111 = $3FF
GPRs (32)
$001F $0020
$0020 3F
Std. IO _______
Registers (64) $005F
$005F
$0060
SRAM (1KB) $0060
3FF
$045F _______
$045F
DRAW THE MEMORY MAP FOR THE DATA ADDRESS SPACE
FOR AVR ATMEGA32 WITH
a. 2KB OF RAM, b. 512 B of RAM, c. 4KB of RAM

How LDS works
ALU Instructions using 2 GPRs
Instructions using 1 GPR
Instructions that Affect Flag Bits
Data Address Space
General RAM EEPROM Timers

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Example: Write a program that adds the contents of the PINC IO
Space R0
R1
R2
$0000 Other
$0001 General register to the contents of PIND andInterrupt
OSC stores
Unit
the result
Ports in location 0x90
Peripherals
OUT
IN (IN(OUT toIO
from IOlocation)
location)
...
Purpose
of the SRAM
...
Registers R31
$001F I/O Address I/O
TWBR
Solution:
$00
OUT IOAddr,Rd
PINS
;[addr]=Rd
IN Rd,IOaddress
Names of;Rd = [addr]
$0020
TWSR $01
Standard I/O Using IO registers
...
...
Registers
SPH $3E
IN R20,PINC ;R20 = PINC
$005F SREG $3F
$0060
General
IN R21,PIND Example:
;R21 = PIND
Example:
purpose
...
RAM ADD R20,R21 ;R20 SPH,R12

OUT = R20 + R21;OUT 0x3E,R12
(SRAM) OUT
IN R1,0x3F,R12
0x3F ;R1;SREG = R12
= SREG
STS 0x90,R20 ;[0x90]
IN = R20
R15,SREG ;IN R15,0x3F
OUT 0x3E,R15;R17
IN R17,0x3E ;SPH = R15
= SPH
$FFFF
Example: Show the status of the C
Status Register (SREG) of 0x38 and 0x2F in the following
C, H, and Z flags after the LDI R16, 0x38 ;R16
he following instructions:
SREG: I T H S V N Z C LDI R17, 0x2F ;R17
Carry
Interrupt oVerflow Zero ADD R16, R17 ;add
Temporary
Sign
Negative Example: Show the status of the C, H, an
;subtract R21Halffrom R20 Data Address
subtraction of 0x73 from 0x52 in the follo
carry N+V Space
$0000 LDI R20, 0x52
$0001 General
Purpose LDI R21, 0x73
...
Registers
R0 $001F SUB R20, R21 ;s
IO Address
ALU R1 $0020 TWBR $00
TWSR $01
R2
Standard IO
...
...
…
Registers
SPH
SREG: I T H S V N Z C $3E
Solution:
Solution:
Solution:
$005F SREG $3F
CPU
Solution: R15 11
$0060
$52
$9C
$A5 0101
R16 0010
1001 1100
1010 1100
0101
d Z flags after the addition $38
$9C 0011
1001 1000 General
-
-- $23
$73
$9C 1001
0010 0111
R17 0011
1100
0011 purpose
...
tions: + + $2F
$64 0110 1111
0100 RAM
PC $DF 1101 1111 R20 = $DF
…
$00
$82
$67
$100 1 00000000
1000
0110
0000 0000
0010
0111 R20 =
R20
R16
R20 == 00
$00
$82
0x67
(SRAM)
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
CC===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20 andbit.
and
the D7 there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C == 00 decoder
because
because the
thereR20
is has
no a value
carry otherthe
beyond than
D7zero after the subtraction.
Instruction
ZZ =
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
to theafter the subtraction.
D4 bit.
H = 1 because there isR31 a borrow
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH===100Register
H
Instruction
becausethe
because
because there
there
R20 is(the
is no
no borrow
borrow from
result) from
has D4
aD4 to D3.
to
value D3.
0 in it after the addition.
Z = 0 because the R16 (the result) has a value other than 0 after the addition.
registers
dd R21 to R20
$FFFF
Example:
AVR Microcontroller and Embedded System Using Show the status of the© C, H, and
2011 Z flags
Pearson Higherafter the
Education,
Assembly and C subtraction of 0x23 from 0xA5 in theRiver,
Upper Saddle following instructions:
NJ 07458. • All Rights
Assembler Directives
.EQU and .SET
 .EQU name = value, #define RLED 13
 Example:
.EQU COUNT = 0x25

LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
 .SET name = value

 Example:
.SET COUNT = 0x25

LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
.INCLUDE
 .INCLUDE “filename.ext” #include <file.h>
M32def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....
.equ INT_VECTORS_SIZE = 42 ; size in words
Program.asm
.INCLUDE “M32DEF.INC”
LDI R20, 10
OUT SPL, R20
.ORG
 .ORG address
00 E205
01 0000
Program.asm 02 0000
03 0000
.ORG 0
LDI R16, 0x25 04 0000
assembler
.ORG 0x7 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 07 E314
08 E321
09 0000
0A 0000
Assembler
Assembly
EDITOR
PROGRAM assembler
myfile.asm
ASSEMBLER
PROGRAM Machine
Language
myfile.eep myfile.hex myfile.map myfile.lst myfile.obj
DOWNLOAD TO DOWNLOAD TO
AVR¶s EEPROM AVR ¶s FLASH
Sample Assembly Program
Flash memory and PC register
00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34
LDI R18, 0x31 02 E321
ADD R16, R17 03 0F01
ADD R16, R18 04 0F02
LDI R17, 11
0516-bit
E01B
ADD R16, R17
STS SUM, R16 06 0F01
HERE:JMP HERE 07 9300
9300
08 0300
0300 RAM EEPROM Timers
09 940C
940C
PROGRAM
0A 0009
Flash0009
ROM ALU
PC: 3
0
9
1
5
2
A
7
4
8
B
6 Data
16bit
16bit CPU Bus

Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
Program ROM Width for the AVR
8-bit = byte
16-bit = word
4 MWords
8 MB
C = 2^22 x 16
C = 2^23 x 8
2^20 = 1 M
2^10 = 1 K
Fetch and execute
Old Architectures
00 E205

01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
Pipelining
 Pipelined Architecture 00
01
E205
E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
CPU Bus
Execute Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
How to speed up the CPU
 Increase the clock frequency
 More frequency  More power consumption &
more heat
 Limitations
 Change the architecture
 Pipelining
 RISC
Changing the architecture
RISC vs. CISC
 CISC (Complex Instruction Set Computer)
 Put as many instruction as you can into the CPU
 RISC (Reduced Instruction Set Computer)
 Reduce the number of instructions, and use your
facilities in a more proper way.
RISC architecture
 Feature 1
 RISC processors have a fixed instruction size. It
makes the task of instruction decoder easier.
 In AVR the instructions are 2 or 4 bytes.
 In CISC processors instructions have different
lengths
 E.g. in 8051
 CLR C ; a 1-byte instruction
 ADD A, #20H ; a 2-byte instruction
 LJMP HERE ; a 3-byte instruction
RISC architecture
 Feature 2: reduce the number of instructions
 Pros: Reduces the number of used transistors
 Cons:
 Can make the assembly programming more difficult
 Can lead to using more memory
 Square root – CISC

 Division - CISC
RISC architecture
 Feature 3: limit the addressing mode
 Advantage
 hardwiring
 Disadvantage
 Can make the assembly programming more difficult
RISC architecture
 Feature 4: Load/Store
LDS R20, 0x200
LDS R21, 0x220
ADD R20, R21
STS 0x230, R20
RAM EEPROM Timers
PROGRAM
Flash ROM ALU
PC: Data
CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
RISC architecture
 Feature
LDS R20, 50x100
(Harvard
; R20 = architecture):
[0x100] separate buses for
ADD R20, R21
opcodes and operands
ADD R20,R21 ; R20 = R20 + R21
LDS R20, 0x100
 Advantage: opcodes and operands can go in and out of the CPU
together.
 Disadvantage: leads to more cost in generalFetch
purpose computers.
Execute
Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus
RISC architecture
 Feature 6: more than 95% of instructions are
executed in 1 machine cycle
RISC architecture
 Feature 7
 RISC processors have at least 32 registers.
Decreases the need for stack and memory usages.
 In AVR there are 32 general purpose registers (R0
to R31)

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Chapter 2

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Introduction to Assembly

The AVR microcontroller

 RISC architecture PROGRAM

LDI (Load Immediate) – load constant values in a

 Rd: R16 to R31 only

Example: Write a program that copies the contents of location 0x80

000000000000 = $000 $0000

a. 2KB OF RAM, b. 512 B of RAM, c. 4KB of RAM

General RAM EEPROM Timers

Program CPU Data

RAM ADD R20,R21 ;R20 SPH,R12

.EQU COUNT = 0x25

 .SET name = value

.SET COUNT = 0x25

myfile.eep myfile.hex myfile.map myfile.lst myfile.obj

16bit CPU Bus

 Square root – CISC

RAM EEPROM Timers

Control bus Control bus

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