Computer Organization

Module V
Prepared By
Asst. Prof. Sherin Thomas
ECE Dept.
MBITS, Nellimattam
Interrupt Initiated I/O
• Interrupt is a hardware signal to the processor from I/O devices
through one of the control line called interrupt-request line.

• The routine executed in response to an interrupt request is called the

interrupt-service routine.
Interrupt Hardware
b) Handling multiple devices

4 methods:

1. Polling 2.Vectored Interrupt 3. Interrupt Nesting 4. Simultaneous Request

1. Polling
• When a device raises an interrupt IRQ bit in Status Register set to1.
• ie, The processor should reads the status registers of each I/O device
associated.
• the first devices which set the IRQ bit is served first which is called polling.
• One of the main disadvantage of polling is always checking the IRQ bit for all
the devices which do not request any interrupt.
2. Vectored Interrupt

• A device requesting an interrupt can identify itself by sending a special code to

the processor over the bus.

• This enables the processor to identify individual devices even if they share a
single interrupt-request line.
3. Interrupt Nesting

To implement this scheme, priority level can be assigned to the processor that can be changed by the
program.

Each of the interrupt request lines is assigned a different priority level.

Interrupt requests received over these lines are sent to a priority arbitration circuit in the processor.

A request is accepted only if it has a higher priority level than that currently assigned to the processor.
 4. Simultaneous request

INTR is common to all devices.

INTA, is connected in a daisy-chain fashion.
Processor responds to INTR by the devices, by setting the INTA line to 1.
This signal is received by device 1.
Device 1 passes the signal on to device 2 only if it does not require any service.
Therefore, in the daisy-chain arrangement, the device that is electrically closest to the processor has
the highest priority.
The second device along the chain has second highest priority, and so on…
Direct Memory Access

What is Bridge?

Direct Memory Access, or DMA

• Allows transfer of a block of data directly between an external device and the main memory, without continuous intervention by the
processor.
• DMA transfers are performed by a control circuit that is part of the I/O device interface called DMA controller.

• Its operation must be under the control of a program executed by the processor.
• To initiate the transfer of a block of words, the processor sends the starting address, the number of words in the block, and the direction of the transfer.
• On receiving this information, the DMA controller proceeds to perform the requested operation.
• When the entire block has been transferred, the controller informs the processor by raising an interrupt signal.
 DMA controller registers that are accessed by the processor to initiate transfer operations.

Two registers are used for storing the starting address and the word count

The third register contains status and control flags.

Done Flag = 1 means DMA Controller completes its data transfer and is ready to receive another command.
R/W =0 means it’s a write operation, otherwise it’s a read operation.
When IE[Interrupt Enable] is set to 1, it causes the controller to raise an interrupt after it has completed transferring a block of data.
Finally, the controller sets the IRQ bit to 1 when it has requested an interrupt.

Cycle stealing:
Requests by DMA devices for using the bus are always given higher priority than processor requests.
Among different DMA devices, top priority is given to high-speed peripherals such as a disk, a high-speed network interface, or a graphics display device.
Since the processor originates most memory access cycles, the DMA controller can be said to "steal" memory cycles from the processor.
Hence, this interweaving technique is usually called cycle stealing.

Burst Mode
Alternatively, the DMA controller may be given exclusive access to the main memory to transfer a block of data without interruption.
This is known as block or burst mode.
 Standard I/O interfaces
This data path have its controls to transfer data
between Interface and IO device called Port.
Data path

• Provides a storage buffer for at least one word of data

• Contains status flags that can be accessed by the processor to
determine whether the buffer is full or empty
• Contains address-decoding circuitry to determine when it is being
addressed by the processor
• Generates the appropriate timing signals required by the bus control
Ports are of two types: scheme
1. Serial port • Performs any format conversion that may be necessary to transfer
data between the bus and the I/O device, such as parallel-serial
2. Parallel port
conversion in the case of a serial port
Serial Port Parallel Port
A serial port transmits and A parallel port transfers data in
receives data one bit at a the form of a number of bits (8 or
time. 16) simultaneously to or from the
device

In serial port, it is much more In parallel port, the connection between

convenient and cost-effective. the device and the computer uses a
multiple-pin connector and a cable with as
many wires.
 PARALLEL PORT

Keyboard Is Connected To A Processor Using A Parallel Port

On the processor side we have: On the keyboard side of the interface:

- Data lines. - Encoder circuit which generates ascii code for the key pressed.
- Address lines - Debouncing circuit which eliminates the effect of multiple key press.
- Control or R/W line. - Data lines contain the code for the key.
- Master-ready signal and - Valid line changes from 0 to 1 when the key is pressed. This causes the code to
- Slave-ready signal. be loaded into DATAIN and SIN[Status IN] to be set to 1.
- SIN cleared to 0 when processor reads the contents of DATAIN register.
Interface circuit is connected to an asynchronous bus on which transfers are
controlled using Master-ready and Slave-ready signals.
Printer Is Connected To A Processor Using A Parallel Port

• On the printer side:

- Idle signal line which the printer asserts when it is ready to accept a character.
- This causes the SOUT flag to be set to 1.
- This Flag is set to zero when new character is loaded into DATAOUT register by the processor.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a new character on the data lines.
SERIAL PORT
Serial port is used to connect the processor to I/O devices that require transmission of data one
bit at a time.
Serial port communicates in a bit-serial fashion on the device side and bit parallel fashion on the
bus side.
Serial interfaces require fewer wires, and hence serial transmission is convenient for connecting
devices that are physically distant from the computer.
Speed of transmission of the data over a serial interface is known as the ―bit rate.
• Input shift register accepts input one bit at a time from the I/O device.
• Once all the 8 bits are received, the contents of the input shift register are loaded in parallel into
DATAIN register.
• The input shift register can start receiving another set of 8 bits from the input device after
loading the contents to DATAIN, before the processor reads the contents of DATAIN. This is
called as double- buffering.
Tristate Buffer

• Output data in the DATAOUT register are loaded into the

output shift register.
• Bits are shifted out of the output shift register and sent
out to the I/O device one bit at a time.
 Standard I/O Interfaces
•It’s not practical to design a different interface for every combination of an I/O device and a computer.
•A practical approach is to develop standard interfaces and protocols.

A number of standards have been developed for the expansion bus.

•Three widely used bus standards:
PCI (Peripheral Component Interconnect)
SCSI (Small Computer System Interface)
USB (Universal Serial Bus)
PCI Bus •Devices connected to the PCI bus appear to the processor as if they were connected
directly to the processor bus.
•They are assigned addresses in the memory address space of the processor.

The PCI bus is designed primarily to support burst mode data transfer ie, data are
transferred in blocks than a single word.

At any given time, one device is the bus master.

It has the right to initiate data transfers by issuing read and write commands.
A master is called an initiator in PCI terminology.
This is either a processor or a DMA controller.

•The addressed device that responds to read and write commands is called a target.
 The main bus signals used for transferring data are listed in the following table.

Signals whose name ends with the symbol # are asserted when in the low- voltage state.
The main difference between the PCI protocol with others is that in addition to a Target-ready signal, PCI also
uses an Initiator ready signal, IRDY #.

Example:
Consider a bus transaction in which the processor reads four 32-bit words from the memory.
•In this case, the initiator is the processor and the target is the memory.
•A complete transfer operation on the bus, involving an address and a burst of data, is
called a transaction.
A clock signal provides the timing reference used to coordinate different phases of a transaction.
All signal transitions are triggered by the rising edge of the clock.
Read Operation on the PCI Bus
 SCSI Bus [SCSI stands for Small Computer System Interface]
It refers to a standard bus defined by the American National Standards Institute (ANSI) under the designation X3.131.

 Devices connected to the SCSI bus are not part of the address space of the processor in the same way as devices
connected to the processor bus.
The SCSI bus is connected to the PCI bus through a SCSI controller.
This controller uses DMA to transfer data packets from the main
memory to the device, or vice versa.
 A controller connected to a SCSI bus is one of two types - an
initiator or a target.
 An initiator(SCSI controller) has the ability to select a particular
target and to send commands specifying the operations to be
performed.
 The disk controller operates as a target. It carries out the commands
it receives from the initiator.
The processor sends a command to the SCSI controller, which causes the following sequence of events to
take place:
Initiator --- SCSI Controller Target ----- Disk Controller

1. The SCSI controller, acting as an initiator, contends for control of the bus.

2. When the initiator wins the arbitration process, it selects the target controller and hands over control of the bus to it.

3. The target starts an output operation; in response to this, the initiator sends a command specifying the required read
operation.

4. The target, realizing that it first needs to perform a disk seek operation, sends a message to the
initiator indicating that it will temporarily suspend the connection between them. Then it releases
the bus.
5. The target controller sends a command to the disk drive to move the read head
to the first sector involved in the requested read operation. Then, it reads the data
stored in that sector and stores them in a data buffer.
When it is ready to begin transferring data to the initiator, the target requests
control of the bus. After it wins arbitration, it reselects the initiator controller, thus
restoring the suspended connection.

6. The target transfers the contents of the data buffer to the initiator and then suspends the connection again. Data are
transferred either 8 or 16 bits in parallel, depending on the width of the bus.

7. The target controller sends a command to the disk drive to perform another seek operation. Then, it transfers the
contents of the second disk sector to the initiator, as before. At the end of this transfer, the logical connection between
the two controllers is terminated.

8. As the initiator controller receives the data, it stores them into the main memory using the DMA approach.

9. The SCSI controller sends an interrupt to the processor to inform it that the requested operation has been completed.
 Universal Serial Bus (USB)

Universal Serial Bus (USB) is an industry standard developed through a collaborative effort of several computer and
communications companies, including Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, Nortel Networks, and Philips.

USB is simple, low cost mechanism to connect devices like keyboards, microphones, cameras, speakers etc. to the computer.

The USB supports two speeds of operation, called low-speed (1.5 megabits/s) and full speed (12 megabits/s).
The most recent revision of the bus specification (USB 2.0) introduced a third speed of operation, called high-speed (480
megabits/s).
USB Architecture:
To accommodate a large number of devices that can be added
or removed at any time, the USB has the tree structure as
shown in the Figure.

Each node of the tree has a device called a hub, which acts as
an intermediate control point between the host and the I/O
devices.
A root hub connects the entire tree to the host computer.
This is responsible for all the transactions. It acts as the controller.

The leaves of the tree are the I/O devices being served (for
example, keyboard, speaker, or digital TV), which are called
functions in USB terminology
USB Protocols:
All information transferred over the USB is organized in packets, where a packet consists of one or more bytes of
information.
The information transferred on the USB can be divided into two broad categories:

1. Control Packet
Control packets perform tasks such as addressing a device to initiate data transfer, acknowledging that data have been
received correctly, or indicating an error. 

2. Data Packet: Data packets carry information that is delivered to a device.

Packet Fields
 The first field of any packet is called the packet identifier, PID, which identifies the type of that packet.
 There are four bits of information in this field, but they are transmitted twice. The first time they are sent with their true
values, and the second time with each bit complemented, as shown in Figure (a). This enables the receiving device to
verify that the PID byte has been received correctly.
All information transferred over the USB is organized in packets, where a packet consists of one or more bytes of
information.
 Packet Transmission

The host computer sends a token packet of type OUT to the

hub, followed by a data packet containing the output data.
The PID field of the data packet identifies it as data packet
number 0.

The hub verifies that the transmission has been error free by
checking the error control bits, and then sends an
acknowledgment packet (ACK) back to the host.

The hub forwards the token and data packets downstream. All
I/O devices receive this sequence of packets, but only the
device that recognizes its address in the token packet accepts
the data in the packet that follows.

After verifying that transmission has been error free, it sends an

ACK packet to the hub.

Successive data packets on a full-speed or low-speed pipe carry the numbers

0 and 1, alternately. This simplifies recovery from transmission errors.
If a token, data, or acknowledgment packet is lost as a result of a transmission
error, the sender resends the entire sequence.
MEMORY HIERARCHY

Cache
•The next level of hierarchy is processor cache, holds copies of instructions and
data stored in much larger memory that is provided externally.
•If the processor requests data that is available in the cache, it is returned quickly.
This is called a cache hit.
•Otherwise, the processor retrieves the data from main memory. This is called a
cache miss.
• If the cache hits most of the time, then the processor seldom has to wait for the
slow main memory, and the average access time is low..
Main Memory
•The next level in the hierarchy is called the main memory.
•The main memory is much larger but significantly slower than the cache
memory.
•The access time for the main memory is about ten times longer than the
access time for the cache.
Hard Disk, Or Hard Drive
•The third level in the memory hierarchy is the hard disk, or hard drive.
•Computer systems use the hard disk to store data that does not fit in main
memory.
•The hard disk provides an illusion of more capacity than actually exists in the
main memory. It is thus called virtual memory
•Disk drives provide a huge amount of inexpensive storage. They are very slow
compared to the semiconductor devices used to implement the main memory
MEMORY HIERARCHY INCLUDING
DIFFERENT LEVELS OF CACHE
MEMORY CHARACTERISTICS
Other Characteristics
 MEMORY SYSTEM PERFORMANCE ANALYSIS
•Memory system performance metrics are
miss rate or hit rate and average memory access time.

Miss and hit rates are calculated as:

 Average memory access time (AMAT)

It is the average time a processor must wait for memory per load or store
instruction. In the typical computer system the processor first looks for the data
in the cache. If the cache misses, the processor then looks in main memory. If
the main memory misses, the processor accesses virtual memory on the hard
disk. Thus, AMAT is calculated as
 SEMICONDUCTOR MEMORIES

•Semiconductor memory is fabricated on silicon chip.

•Semiconductor memory preferred due to its low cost.

Characteristics of semiconductor memory

• low cost, high density (bits per chip), and ease of use.
•Memory can be graded in terms of capacity and speed of access.
Volatile[RAM]
Whose contents can be read and also written to is called volatile memory.
In a volatile memory, information decays naturally or is lost when electrical power is
switched off.
Examples of this type are
DRAM and SRAM.
Non-Volatile[ROM]

Those whose contents can only be read.

Some memory’s contents may be permanent, while other memory chips may be
removed from the computer and reprogrammed.
Information once recorded remains without deterioration until deliberately changed;
no electrical power is needed to retain information.
Examples of this type are ROM,
PROM, EPROM and EEPROM.
Random Access Memory (RAM)
Characteristics
1. It is possible both to read data from the memory and to write new data into the
memory easily and rapidly.
Both the reading and writing are accomplished through the use of electrical signals.

2. It is volatile.
A RAM must be provided with a constant power supply.
If the power is interrupted, then the data are lost.
Thus, RAM can be used only as temporary storage.

The two traditional forms of RAM used in computers are DRAM and SRAM.
Static Random Access Memory (SRAM)

SRAM is a digital device.

In a SRAM, binary values are stored using traditional flip-flop logic-gate
configurations .
1.Consist of circuits that are capable of retaining their state as long as the power is
applied, so called static memories.
2.Volatile memories, because their contents are lost when power is interrupted.
3.Access times of static RAMs are in the range of few nanoseconds.
4.However, the cost is usually high.
A single SRAM cell is shown in the below figure.
Two inverters are cross-connected to form a latch.

The latch is connected to two bit lines by transistors T1 and T2.

These transistors act as switches that can be opened or closed

under the control of the word line.

When the word line is at ground level, the transistors are turned
off and a latch retains its state.

Wordline

Let us assume that the cell is in state 1 if the logic value at point X is 1 and at point Y is 0. This state is maintained as long as
the signal on the word line is at ground level.
 Read Operation
•In order to read the state of the SRAM cell, the
word line is activated to close switches T1 and
T2.
Word line = 1, access transistors are ON.
•If the cell is in state 1, the signal on bit line
b is high and the signal on bit line b‘ is low.
The opposite is true if the cell is in state 0.
Thus, b and b‘are compliments of each other.
•Sense/Write circuits at the end of the bit lines monitor the state of b and b‘ and
set the output accordingly. It compares the difference between bit b and bit b’.
• if bit b > b’, output is 1
• if bit b < b’, output is 0
Write operation

•Word line = 1, access transistors are ON.

• Place appropriate values on the bit line b and
its compliment on b‘.
•This forces the cell into the corresponding
state. Data in latch overwritten with new value.
•The required signals on the bit lines are
generated by the Sense/ Write circuit.
•Dynamic Random Access Memory

SRAMs are fast but costly. Less expensive RAM can built using capacitors called DRAM

Such cells do not retain their state indefinitely; hence they are called dynamic RAMs

Information are stored in dynamic memory cell in the form of charge on a

capacitor.
This charge can be maintained for only tens of milliseconds.

Since the cell is required to store information for a much longer time, its
contents must be periodically refreshed by restoring the capacitor charge to
its full value.
 A single transistor dynamic cell is shown in the figure given below

It consists of a capacitor C, and a transistor T. Hence the information stored in the cell
can be retrieved correctly only if it is read before the charge on the capacitor drops
below some threshold values.
Dram Operation
•Make the Word line active when bit read or written
•Transistor switch closed (current flows)
Read Operation
•During a read operation the transistor in a selected
cell is turned on.

•A sense amplifier connected to the bit line detects

whether the charge stored on the capacitor is above
the threshold value.
If so it drives the bit line to a full voltage that represents the logic value 1
This voltage recharges the capacitor to a full charge that
corresponds to logic value 1.
•Thus reading the contents of the cell automatically refreshes the
contents.
•All cells in a selected row are read at the same time. This
refreshes the contents if the entire row.
 Write Operation

•If we want to write logic high (1) to a

memory cell make the Voltage to bit line is
high. This voltage is transferred to the
capacitor and causes a known amount of
charge to be stored in the capacitor.

•If we want to write logic low (0) to a memory

cell make the Voltage to bit line is low. Then
the capacitor starts discharging which means a
low is stored in the capacitor.
Memory comparison
---Both volatile
—Power needed to preserve data
Dynamic cell[DRAM]
—Simpler to build, smaller
—More dense
—Less expensive
—Needs refresh
—Larger memory units
Static[SRAM]
—Faster
—Cache
ROM [Read-only Memories]

•A memory is called a read-only memory, or

ROM, when information can be written into
it only once at the time of manufacture.
•Figure shows a possible configuration for a
ROM cell.
•Write Operation
A logic value 0 is stored in the cell if the
transistor is connected to ground at point P;
otherwise, a 1 is stored. The bit line is
connected through a resistor to the power
supply.
•Read Operation

To read the state of the cell, the word line is

activated to close the transistor switch. As a
result, the voltage on the bit line drops to
near zero if there is a connection between the
transistor and ground, indicating a 0

If there is no connection to ground, the bit

line remains at the high voltage level,
indicating a 1.

A sense circuit at the end of the bit line

generates the proper output value.
The contents of a ROM can be indicated using dot notation.

Figure shows the dot notation for a 4-word into 3-bit ROM containing the data
A programmable ROM [PROM]

•A programmable ROM places a transistor in every bit cell but provides a way to
connect or disconnect the transistor to ground.

•Some ROM designs allow the data to be loaded by the user, thus providing a
programmable ROM (PROM). Programmability is achieved by inserting a fuse
at point P in the above Figure.
•The user programs the ROM by
applying a high voltage across the
bitline to selectively blow fuses.

•If the fuse is present, the

transistor is connected to GND
and the cell holds a 0.

•If the fuse is destroyed, the transistor is

disconnected from ground and the cell
holds a 1. This is also called a onetime
programmable ROM, because the fuse
cannot be repaired once it is blown.
Erasable PROMs [EPROM]

•Another type of ROM chip provides an even higher level of convenience.

•It allows the stored data to be erased and new data to be written into it.
•So this is an erasable, reprogrammable ROM is usually called an EPROM.
•Memory changes and updates can be easily made.
•. Erasing can be done by exposing the chip to ultraviolet light, which erases the
entire contents of the chip.
•To make this possible, EPROM chips are mounted in packages that have
transparent windows.
EPROMs, replace the nMOS transistor and fuse with a floating-gate transistor.
Flash memory works by adding (charging) or removing (discharging) electrons to and from a floating gate. A bit's 0 or 1
state depends upon whether or not the floating gate is charged or uncharged. When electrons are present on the floating
gate, current can't flow through the transistor and the bit state is 0. This is the normal state for a floating gate transistor,
when a bit is programmed. When electrons are removed from the floating gate, current is allowed to flow and the bit state
is 1.
Electrically erasable PROMs (EEPROMs, pronounced “e-e-proms” or
“double-e proms”) and
Flash memory use similar principles but include circuitry on the chip for
erasing as well as programming, so no UV light is necessary.
• EEPROM bit cells are individually erasable; Flash memory erases larger blocks
of bits and is cheaper because fewer erasing circuits are needed.
INTERNAL ORGANIZATION OF SEMICONDUCTOR MEMORY CHIP

The memory is organized as a two-dimensional

array of memory cells
The memory reads or writes the contents of one of the
rows of the array
This row is specified by an Address.
•The value read or written is called Data. Each row of data
is called a word
An array with N-bit addresses and M-bit data has 2N rows and
M columns.
•Figure shows a memory array with two address bits and three data bits.
Bit Cells

Memory arrays are built as an array of bit cells, each of which stores 1 bit
of data.
Figure shows that each bit cell is connected to a wordline and a bitline.

For each combination of address bits, the memory asserts a single wordline that
activates the bit cells in that row.

When the wordline is HIGH, the stored bit transfers to or from the bitline.

•Otherwise, the bitline is disconnected from the bit cell.

ORGANIZATION OF SEMICONDUCTOR MEMORY CHIP

Figure shown below is an example of a very small memory chip consisting of

16 words of 8bits each.
This is referred to as a 16 X 8 organization.
Read Operation:
During a Read operation, these circuits sense, or read, the information stored in the
cells selected by a word line and transmit this information to the output data lines.

Write Operation:
During a Write operation, the Sense/Write circuits receive input information from the
bidirectional data lines and store it in the cells of the selected word.