Project no 19:

Project problem statement:

Suppose you have 4x16 decoder constructed with two 3x8 decoders (See Figure below). Design,
implement, and synthesize the decoder. Also, check whether any input line is affected by a stuck fault.

Decoder:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of these
outputswill be active High based on the combination of inputs present, when the decoder is enabled.
3:8 Decoder
decoder circuit gives 8 logic outputs for 3 inputs. The circuit is designed
with AND NAND COMBINATIONS. It takes 3 binary inputs and activates one of the eight outputs. It will only
workswhen Enable is high.

Circuit diagram of 3:8 decoder

Circuit design:

A decoder circuit of the higher combination is obtained by adding two or more lower combinational circuits. 4
to 16 decoder circuit is obtained from two 3 to 8 decoder circuits or three 2 to 4 decoder circuits.
When two 3 to 8 Decoder circuits are combined the enable pin acts as the input for both the decoders. When
enable pin is high at one 3 to 8 decoder circuits then it is low at another 3 to 8 decoder circuit.

Circuit diagram of 4:16 decoder

5. Simulation Procedure-
At first, we have implemented the design for 3 to 8 decoder in which we
are going to use two of them in building 4 to 16 decoder.
Implementation of 3 to 8 decoder: Verilog code

Next, we checked the code whether it is syntactically correct

or not, and here is the output.
So we added two of them in 4 to 16 decoder to meet our design
implementation.
Now let's write the code for 4 to 16 decoder using two 3 to 8
decoders.
XST has also been synthesized along with it.
This is how it looks in RTL schematic circuit diagram:

Technology schematic diagram of 4 to 16 decoder:

Now let's simulate the Verilog code we have written for 4 to 16
decoder, Means lets write the code for the testbench:
Let's simulate the behavioural model and let's look at the output
we get from it using the testbench:

Output:
Let's implement the design: Translate, Map, Place and Route has
been successfully completed.
We have successfully done the configure target device:
We generated the program code for the 4 to 16 decoder:

Hence by this we completed our FPGA simulation part. Thank you.