PROBLEM

Designing Procedure

The steps for design procedure is as follows:

• We designed the schematic Verilog diagram for and, or, not, xor and xnor gates.
• After designing the schematic verilog in Xilinx 14.7 ISE generate the HDL code for those gates
using the option to generate HDL functional code.
• Then create the testbench for the schematic verilog file with 4 instances, i.e.
• input1=0, input2=0; input1=0, input2=1; input1=1, input2=0; input1=1, input2=1
• Write the code for stuck at faults in different files for each case.
• Add the outputs of stuck at faults to testbench so that it is visible when we simulate it.
 Implementation

Steps for implementation:

 Check the simulation check-box.
 Click behavorial syntax check to check for any syntax errors.
 Then simulate the code by clicking on simulation option.
 We can produce RTL Schematic and Technology Schematic diagrams in the implementation
part.
 The generate HDL functional model, HDL Instantiation template option to generate Behavorial
code from schematic is also available in Implementation part.
 Solution

 For normal cases the outpt matches with the truth table
 For Stuck-at-faults it gives wrong outputs, sometimes.
Module level diagrams
Module level diagrams
 Timing diagram

AND OR
 Timing diagram

NOT XOR XNOR

 Schematic Diagrams

AND OR
 Schematic Diagrams

NOT XOR XNOR

 Conclusion

In this project, we implemented AND, OR, NOT, XOR and XNOR Gates using NOR gate through the FGPA
Package of XILINIX ISE simulator and tested it for stuck-at-faults. NOR gate has many applications in the
digital world. NOR Gates are used in combinational circuits like Half-adder, Full-adder, MUX etc.
These are also can be Used in Sequential circuit to make level and edge triggered flipflops, which are in
turn used in memory devices, shift registers etc.

A digital circuit is tested for faults to check whether the implemented circuit is good to use or not. A
faulty circuit functions improperly and therefore, in a large and practical scale cost of not testing is too
high. In this project we have tested our model for stuck-at faults. A basic method of testing is applying a
set of inputs observing the output.

Finally, we would like to state that, on successfully Implementing and testing our HDL Verilog model we
detected no stuck-at fault in our model. And all the implementations of AND, OR, NOT, XOR, XNOR Gates
are working properly now.
Thank you