A PROJECT ON

GSM BASED SECURITY SYSTEM FOR BANKS

USING ARM PROCESSOR

Under the guidance of PRESENTED BY

Sri B.N. SRINIVASA RAO D.DIVAKAR BABU(07811A0421)
D.VINOD KUMAR(07811A0429)
D.PURUSOTHAM(07811A0428)
Associate Professor E.C.E L.SUDHEER KUMAR(07811A0463)
 CONTENTS
 INTRODUCTION

 ABOUT THE PROJECT

 BLOCK DIAGRAM

 HARDWARE REQUIREMENTS

 SOFTWARE REQUIREMENTS

 CONCLUSION
INTRODUCTION
BLOCK DIAGRAM
 HARDWARE REQUIREMENTS
 ARM Microcontrollers(LPC2129)

 GSM MODEM

 MOTION SENSOR

 MAX232

 LCD

 POWER CIRCUIT
POWER CIRCUIT
 MOTION SENSORS

IR TRANSMITTER IR RECEIVER
LCD
MAX 232
MAX 232 INTERFACING
GSM MODEM
GSM MODEM
ABOUT THE ARM PROCESSOR

Advanced Risc Machine

BRIEF HISTORY OF ARM
 ARM is short for Advanced RISC Machines Ltd.
 Founded 1990, owned by Acorn, Apple and VLSI
Known before becoming ARM as computer
manufacturer
 Acorn which developed a 32-bit RISC processor for it’s
own use (used in Acorn Archimedes)
WHY ARM HERE
 ARM is one of the most licensed and thus widespread
processor cores in the world
 Used especially in portable devices due to low power
consumption and reasonable performance (MIPS / watt)
 Several interesting extensions available or in
development like Thumb instruction set and Jazelle Java
machi
ARM FEATURE
 RISC(Reduced Instruction Set Computer) architecture
􀂄 General purpose 32-bit microprocessors
􀂄 Very low power consumption and price
􀂄 Big/Little Endian Mode
􀂄 Intel x86 – Little Endian
􀂄 Motorola – Big Endian
􀂄 Fast Interrupt Response
􀂄 FIQ Mode
􀂄 Excellent High Level Language Support
􀂄 C Language
􀂄 Auto Increment/Decrement addressing mode
􀂄 Simple and powerful Instruction Set
􀂄 Load/Store multiple instructions
􀂄 Conditional execution
ARM® JAZELLE TECHNOLOGY

 􀂄 The ARM Jazelle technology provides a highly-

optimized implementation of the Java Virtual Machine
(JVM), speeding up execution times and providing
consumers with an enriched user experience on their
mobile devices.,
ARM ARCHITECTURE
ARM:
 32-bit RISC-processor core (32-bit instructions)
 37 pieces of 32-bit integer registers (16 available)
 Pipelined (ARM7: 3 stages)
 Von Neuman-type bus structure (ARM7), Harvard
(ARM9)
 8 / 16 / 32 -bit data types
 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
 Simple structure -> reasonably good speed / power
consumption ratio
HAYWARD ARCHITECTURE
 In harward architecture we Are having two different
memories are there to access Instructions and data.
 Here we can increase the throughput because while you
are executing one instruction you can fetch one more
instruction
VON NEUMANN ARCHITECTURE
 von Neumann architecture is a model for a computing
machine that uses a single storage structure to hold both
the set of instructions on how to perform the
computation and the data required or generated by the
computation.
PROCESSOR MODES
 SOFTWARE REQUIREMENTS

 KEIL MICRO VISION 4

 CODE SIMULATOR
 CONCLUSION
 Alert police without giving thief any clue
 future 3G -transfer a live video
QUERIES ??