SHARED MEMORY ATM SWITCH

ARCHITECTURE

JIVASINGH
 ATM Switch Architectures
• An ATM Switch is used to transfer cells from its
incoming links to out going links. This is know as
switching function.

• These ATM switches can be grouped into three

classes, namely ,
• Space Division Switches
• Shared memory switches
• Shared medium switches
• A generic model of ATM Switch consists N input and N
output ports.

• Each input port have a finite capacity buffer where cells

wait until they are transferred to their destination output
ports.

• An ATM switch is referred to as an output buffering switch

if only if its output ports are equipped with buffers.

• The input ports are connected to their out put ports via the
switch fabric. It is equipped with a CPU, which is used to
carry out signalling and management functions.
 Shared memory switch
• Shared memory is used to store all the cells coming in
from the input ports.
• It can read and write at the same time.
• Shared memory is organized into linked lists one per
output port.
• At the beginning of the slot all the input ports that
have a cell, write into the shared memory. At the same
time all the output ports with a cell to transmit read the
cell from the top of their linked list and transmit it out .
• If N is the no of input/output ports then in one
slot upto N cells can be written and
transmitted.If the speed of transmission is V
then the required bandwidth is 2NV.

• An output port gets hot when a lot of

incoming traffic goes to a particular port. As a
result queue of the port takes lot of the
shared memory leaving little space for other.
 Cell loss
• Cell loss occurs when a cell arrives at a time
when the shared memory is full.i.e it contains
B cells.

• Cell loss occurs when a cell with destination

port i arrives at a time when the total no of
cells queued for this port is Bi i.e.queue is full.
Hitachi shared memory switch
 Hitachi shared memory switch
• Proposed by Hitachi.
• First, cells are converted from serial to parallel
and header conversion takes place.
• Cells from all the input ports are multiplexed
and written into shared memory,
• For each linked list there is a pair of address
registers(one to write WA one to read RA).
• The WA reg for the linked list contains the
address of last cell of the list, which is always
empty . The incoming cell is written in that
address . At the same time WA is updated from
IABF, which keeps a pool of empty buffer
locations.
• At each slot a packet from each list is identified
through the content of RA reg retreived,
demultiplexed and transmitted. The empty
buffer is returned to pool and RA is updated
with next cell address of the linked list.
 Bit slicing method

• To reduce bandwidth bit slicing method is used,

• Here a cell in the linked list is stored in K

fragments over K shared memories . If we have
N links and speed of transmission is V then
required bandwidth is 2NV/K.
.
• Shared memory switch architecture has also been used
in non blocking switch with output buffering.

• If there is a dedicated buffer for each out port free

space in one port cant be used for other.
• This may result in the poor utilization of the buffer
space.

• This can be solved by using shared memory switch to

serve a number of ports.
THANK YOU