Advance Digital

Electronics

WEEK 05 & 06

1
 PERFORMANCE
CHARACTERISTICS: SCHOTTKY
TTL
• THE 74S SERIES SPECS:
• VOH=2.7V
• VIH=2.0V
• VOL=0.5V
• VIL=0.8V
• tp= 3ns
• PD=20mW
• Delay Power Product=60pJ
THE LOW POWER SCHOTTKY TTL
 THE LOW POWER SCHOTTKY TTL:
74LS
• RESISTANCES USED ARE ABOUT 10 TIMES LARGE
THAN 74S FAMILY THUS POWER DISSIPATION IS
ABOUT TENTH OF THAT OF THE 74S FAMILY (2mW
VERSUS 20mW PER GATE)
• BY INCREASING RESISTANCES, SPEED WOULD
DECREASE…..HENCE SEVERAL MEASURES HAVE
BEEN TAKEN TO INCREASE THE SPEED:
1) THE MULTI-EMITTER TRANSISTOR HAS BEEN
REMOVED! SCHOTTKY DIODES OCCUPY LESSER
AREA! NO NEED FOR THE MULTI-EMITTER AS Q2 IS
NOT SATURATING HERE!
2) D3 AND D4 HAVE BEEN ADDED TO INCREASE THE
SPEED!
 THE LOW POWER SCHOTTKY TTL:
74LS
• HOW?
THEY ASSIST IN SPEEDING UP THE TURN OFF OF Q4 AND TURN ON
OF Q3!
AS GATE INPUT IS RAISED, Q2 STARTS TO TURN ON, SOME OF ITS
COLLECTOR CURRENT WILL FLOW THRU THE DIODE D3 AND
WOULD MAKE D3 CONDUCT. ITS CONDUCTION WOULD
REMOVE THE BASE STORED CURRENT OF Q4.
SOME OF THE EMITTER CURRENT OF Q2 WILL BE SUPPLIED TO
THE BASE OF Q3 CAUSING IT TO TURN ON FASTER, SOME OF
THE COLLECTOR CURRENT OF Q2 WILL ALSO FLOW THRU
DIODE D4 AND THIS WILL BE FORWARD BIASED. IT WILL
SUPPLY AN ADDITIONAL DISCHARGE PATH FOR THE LOAD
CAPACITANCE HENCE SHORTEN THE HIGH TO LOW
TRANSITION TIME.
BOTH D3 AND D4 SHALL REMAIN CUT-OFF UNDER THE STATIC
CONDITIONS.
THE TTL FAMILY PERFORMANCE
COMPARISON
Emitter Coupled Logic (ECL)
 THE EMITTER COUPLED LOGIC (ECL):

• ONE OF THE FASTEST LOGIC FAMILIES.

• HIGH SPEED IS ACHIEVED BY:
1. KEEPING TRANSISTORS OUT OF SATURATION

2. KEEPING THE LOGIC SWING SMALL I.E

AROUND 0.8 V!
• THE SATURATION IS PREVENTED NOT BY
SCHOTTKY ARRANGEMENT BUT BY USING A
DIFFERENTIAL PAIR AS A CURRENT SWITCH!
THE EMITTER COUPLED LOGIC (ECL):
BASICS
 THE EMITTER COUPLED LOGIC (ECL):

• BASED UPON A CURRENT STEERING SWITCH.

• IT CAN BE CONVENIENTLY REALIZED BY A
DIFFERENTIAL PAIR.
• THE PAIR IS BIASED USING A CONSTANT
CURRENT SOURCE.
• CURRENT ‘I’ CAN BE STEERED TO EITHER Q1 OR
Q2, UNDER THE CONTROL OF THE INPUT SIGNAL
‘V1’.
• IF V1 >VR BY 4VT≈100mV Q1 CONDUCTS.
• IF VR >V1 BY 4VT≈100mV QR CONDUCTS.
• ALL THE CURRENT ‘I’ WILL BE SUPPLIED BY THE
CONDUCTING TRANSISTOR.
 THE EMITTER COUPLED LOGIC (ECL):

• THE OUTPUT VOLTAGE=Vcc-IRc.

• OBVIOUSLY, THE LOGIC FUNCTION AVAILABLE IS
THE INVERTER AND ITS COMPLIMENT AT THE
SAME TIME!
• THERMAL VOLTAGE: A CONSTANT WHOSE
VALUE IS GIVEN BY VT=kT/q
• k=Boltzman’s Constant 1.32x10-23.
• T=Absolute Temperature=273+Degree C
• q=Magnitude of the electronic charge 1.60x10-19 C.
• The value of VT at room temperature is about 25mV.
 THE EMITTER COUPLED LOGIC (ECL):

OBSERVATIONS:
1. DIFFERENTIAL NATURE OF THE CIRCUIT MAKES
IT LESS SUSCEPTIBLE TO PICKED UP NOISE, THE
COMMON MODE REJECTION PROPERTY OF THE
DIFFERENTIAL PAIR.
2. CURRENT DRAWN FROM SUPPLY REMAINS
CONSTANT, NO CURRENT SPIKES DURING
SWITCHING, CIRCUIT MORE IMMUNE TO NOISE!
3. THE LOGIC LEVELS ARE REFERENCED TO Vcc
HENCE A NEGATIVE SUPPLY SYSTEM CAN BE
ADOPTED WITH THE SAME CIRCUIT. VEE=-VE
VOLTAGE SOURCE SO VOH=0V, VOL=-IRc V.
THE EMITTER COUPLED LOGIC (ECL):

4. SOME MEANS HAS TO BE PROVIDED TO MAKE THE

OUTPUT VOLTAGE LEVELS COMPATIBLE TO
DRIVE THE LOAD. THIS ARRANGEMENT IS
PROVIDED IN PRACTICAL ECL CIRCUITS THRU A
‘LEVEL SHIFTING’ ARRANGEMENT.
5. THE AVAILABILITY OF COMPLIMENTARY
OUTPUTS CONSIDERABLY SIMPLIFIES THE LOGIC
DESIGN WITH ECL.
 THE EMITTER COUPLED LOGIC (ECL):

ECL FAMILIES:
ECL 10K AND ECL 100K!
ECL 10K
• tp=2nS
• PD=25mW/Gate
• Delay Power Product=50pJ
ECL 100K
• tp=0.75nS
• PD=40mW/Gate
• Delay Power Product=30pJ
 THE EMITTER COUPLED LOGIC (ECL):

• The ECL 10 K HAS INTENTIONALLY BEEN MADE

SLOWER TO REDUCE SIGNAL COUPLING
PROBLEMS AND CROSSTALK HAZARDS.
• ECL CIRCUITS HAVE BEEN USED IN SSI/ MSI /LSI
AND EVEN VLSI DESIGNS.
THE BASIC ECL 10K CIRCUIT
 THE EMITTER COUPLED LOGIC (ECL):

• CONSISTS OF THREE PARTS.

• Q1, D1, D2, R1, R2 AND R3 GENERATES A
REFERENCE VOLTAGE VR WHOSE VALUE AT
ROOM TEMPERATURE IS -1.32V. THIS REFERENCE
VOLTAGE IS CHANGED IN A PRE-DETERMINED
MANNER WITH REFERENCE TO TEMPERATURE
CHANGES SO THAT THE ‘NOISE MARGINS’
REMAIN ALMOST CONSTANT.
• THIS VOLTAGE REMAINS ALMOST CONSTANT
WITH REFERENCE TO CHANGES IN THE SUPPLY
VOLTAGE.
 THE EMITTER COUPLED LOGIC (ECL):

• THE SECOND PART IS THE HEART OF THE

CIRCUIT, ‘THE DIFFERENTIAL AMPLIFIER’.
• THE AMPLIFIER IS NOT BIASED BY A CONSTANT
CURRENT SOURCE, BUT THRU A RESISTOR ‘RE’ OF
779Ω!
• THE CURRENT THRU THIS RESISTOR, HOWEVER,
REMAINS ALMOST CONSTANT.
• IF VA & VB BOTH =0V MEANS 0.4V BELOW VR
(LOGIC LEVEL LOW FOR THE CIRCUIT), THE
TOTAL CURRENT ‘I’ SHALL BE SUPPLIED BY QR
HENCE VCQR WILL BE ‘LOW’ AND VCQA/VCQB
WILL BE ‘HIGH’.
 THE EMITTER COUPLED LOGIC (ECL):

• IF VA AND/OR VB=1, MEANS 0.4V ABOVE VR

(LOGIC LEVEL HIGH FOR THE CIRCUIT), QA, QB
OR BOTH SHALL CONDUCT, THUS ‘I’ SHALL BE
SUPPLIED BY QA OR QB OR BOTH, THUS
VCQA/VCQB=LOW AND VCQR WILL BE EQUAL TO
HIGH.
• HENCE VCQA/VCQB PERFORMS THE ‘OR’
OPERATION WHEREAS VCQR GIVES A ‘NOR’
OUTPUT.
• RA AND RB ENSURES THAT UNUSED INPUTS CAN
BE LEFT OPEN, SINCE THE OPEN INPUT WILL
AUTOMATICALLY BE CONNECTED TO NEGATIVE
VCC AND THE CORRESPONDING TRANSISTOR
WOULD REMAIN OFF.
THE EMITTER COUPLED LOGIC (ECL):

 THE THIRD PART CONSISTS OF TWO EMITTER

FOLLOWERS, Q2 AND Q3.
 THESE DON’T HAVE ANY ‘ON-CHIP’ LOAD AND
THEY USUALLY DRIVE LOADS THRU
TRANSMISSION LINES.
 THE EMITTER COUPLED LOGIC (ECL):

• EMITTER FOLLOWERS HAVE TWO PURPOSES:

1. THEY SHIFT THE OUTPUT VOLTAGE LEVEL TO 1
VBE DROP. THUS THE OUTPUT VOLTAGES ARE:
VOL=-1.75V AND VOH=-0.75V, THESE SHIFTED
LEVELS ARE CENTERED AT AROUND -1.32V. THIS
ENSURES THAT ONE GATE CAN DRIVE THE
OTHER!
2. THEY PROVIDE THE GATE WITH LOW OUTPUT
RESISTANCE AND WITH LARGE OUTPUT
CURRENTS REQUIRED FOR CHARGING LOAD
CAPACITANCES.
 THE EMITTER COUPLED LOGIC (ECL):

• THESE LARGE LOAD CURRENTS CAN CAUSE

SPIKES WHAT WOULD BE MAPPED OVER THE
SUPPLY VOLTAGE.
• DUE TO THIS, THE OUTPUT STAGE HAS A
SEPARATE SUPPLY!
• THIS ENSURES THAT THE OUTPUT CURRENT
SPIKES WILL NOT EFFECT THE LOGIC LEVELS
AND THE CRITICAL LOGICAL DECISIONS WILL BE
IMMUNE TO THESE OUTPUT CURRENT SURGES
HENCE FALSE SWITCHING IS PREVENTED IN THIS
MANNER.
THE EMITTER COUPLED LOGIC (ECL): THE
VOLTAGE TRANSFER CHARACTERISTICS
 THE EMITTER COUPLED LOGIC (ECL):

• FOR THE ANALYSIS, WE WILL FURTHER ASSUME

THAT THE SIZE OF THE BJ Ts USED IN ECL ARE
SMALL TO HAVE SMALL CAPACITANCES.
• AN EMITTER CURRENT OF 1mA, CAUSES A VBE OF
ABOUT 0.75 V.
THE ‘OR’ TRANSFER CURVE
 THE OR TRANSFER CURVE

NOISE MARGINS:
VOL+VOH/2=-1.32V=VR
THE OUTPUT LOGIC LEVELS ARE CENTERED
AT THE MIDPOINT OF THE INPUT
TRANSITION BAND, THIS IS AN IDEAL
SITUATION FROM THE POINT OF VIEW OF
NOISE MARGINS.
NMH=VOH-VIH=-0.88-(-1.205)=0.325V
NML=VIL-VOL=-1.435-(-1.77)=0.335V
THE NOR TRANSFER CURVE
 ECL: MANUFACTURER’S SPECS

•TRANSFER CURVES AT VARIOUS TEMPERATURES

ARE PROVIDED BY THE MANUFACTURER.
•AT EACH TEMPERATURE, WORST CASE VALUES FOR
THE PARAMETERS VIL, VIH, VOL AND VOH ARE
PROVIDED.
•MOTOROLA MECL 10,000 AT 250C GIVES:

VIL(max)=-1.475V, VOL(max)=-1.630V
VIH (min)=-1.105V, VOH(min)=-0.980V
•WITH THESE VALUES THE WORST CASE NOISE
MARGINS ARE: NML=0.155, NMH=0.125
•THESE ARE ABOUT HALF THE TYPICAL VALUES WE
HAVE CALCULATED EARLIER!
 ECL: MANUFACTURER’S SPECS

•FAN OUT: IF THE INPUT SIGNAL TO THE ECL GATE IS

LOW THE OUTPUT CURRENT IS EQUAL TO THE
CURRENT THAT FLOWS THRU THE 50kΩ PULL DOWN
RESISTOR, THUS:
I(INPUT LOW)=-1.77+5.2/50,000≈69μA.
•WHEN THE INPUT IS HIGH, THE INPUT CURRENT IS
GREATER BECAUSE OF THE BASE CURRENT OF THE
INPUT TRANSISTOR.
•ASSUMING β=100 WE GET:

IIH=-0.88+5.2/50+4/101≈126μA.
•BOTH OF THESE CURRENTS ARE QUITE SMALL!
ECL: MANUFACTURER’S SPECS
 ECL: MANUFACTURER’S SPECS

•BUTWHY ECL IS CONSIDERED TO BE ONE OF THE

MOST POWER DEMANDING FAMILIES????? DESPITE
OF THE FACT THAT THE INPUT CURRENT OF THIS
LOGIC FAMILY IS QUITE SMALL!
 ECL: MANUFACTURER’S SPECS

•THEFAN-OUT OF ECL IS NOT LIMITED BY THE

DRIVING CURRENT SCENARIO BUT IS RELATED TO
THE SPEED DEGRADATION! (REFERENCE, LOW INPUT
CURRENT!)

•THEDC FAN-OUT CAN BE AS HIGH AS 90 BUT THE AC

FAN-OUT (ACTUAL FAN OUT FOR HIGH SPEED ECL) IS
ONLY AROUND 10!

•MOREOVER, THE OUTPUT RESISTANCE OF ECL IS

VERY SMALL TOO, WHICH ENSURES GREATER
DRIVING CAPABILITIES…….
 ECL: MANUFACTURER’S SPECS

SPEED:
•IT IS MEASURED BY THE DELAY OF THE BASIC GATE
AND THE RISE AND FALL TIMES OF THE OUTPUT
WAVEFORM!
•THE RISE AND FALL TIME OF THE OUTPUT
WAVEFORM IS THE FUNCTION OF THE OUTPUT OR
LOAD CAPACITANCE.
•HENCE THE DELAY IS FUNDAMENTALLY A
COMBINATION OF THE DELAY OF THE BASIC GATE
AND ITS OUTPUT CAPACITANCE (LOAD
CAPACITANCE).
THE END