COMPUTER ORGANIZATION

AND ASSEMBLY LANGUAGE

Lecture 15 & 16
Stacks, Endianness
Addressing Modes
Course Instructor: Engr. Aisha Danish
Stacks
 A stack is an ordered set of elements, only one of which
can be accessed at a time.
 The point of access is called the top of the stack
 The number of elements in the stack, or length of the
stack, is variable
 The last element in the stack is the base of the stack
 Items may only be added to or deleted from the top of the
stack
 A stack is also known as a pushdown list or a last-in-
first-out (LIFO) list
Stacks
Stacks
 A PUSH operation appends one new item to the top of
the stack
 A POP operation removes the top item from the stack
 Binary operators, which require two operands (e.g.,
multiply, divide, add, subtract), use the top two stack
items as operands, pop both items, and push the result
back onto the stack
 Unary operations, which require only one operand
(e.g., logical NOT), use the item on the top of the stack
 Stack Implementation
 The stack is a useful structure to provide as part of a processor
implementation
 One use, is to manage procedure calls and returns
 Stacks may also be useful to the programmer
 The implementation of a stack depends in part on its potential uses
 If it is desired to make stack operations available to the programmer,
then the instruction set will include stack-oriented operations,
including PUSH, POP, and operations that use the top one or two
stack elements as operands
 Because all of these operations refer to a unique location, namely the
top of the stack, the address of the operand or operands is implicit and
need not be included in the instruction. These are the zeroaddress
instructions
 Stack Implementation
 Implementation of a stack requires some set of locations to be used to store the stack elements
 A contiguous block of locations is reserved in main memory (or virtual memory) for the stack

 Most of the time, the block is partially filled with stack elements and the remainder is available

for stack growth

 Three addresses are needed for proper operation, and these are often stored in processor

registers:
Stack pointer (SP)
Contains the address of the top of the stack.
If an item is appended to or deleted from the stack, the pointer is incremented or decremented
to contain the address of the new top of the stack.
Stack base
Contains the address of the bottom location in the reserved block. If an attempt is made to
POP when the stack is empty, an error is reported.
Stack limit
Contains the address of the other end of the reserved block. If an attempt is made to PUSH
when the block is fully utilized for the stack, an error is reported.
Stack Implementation
 Stack Implementation
Stack implementations have two key attributes:
Ascending/descending
 Ascending stack grows in the direction of ascending addresses, starting from a
low address and progressing to a higher address
 SP is incremented when items are pushed
 Decremented when items are pulled
 A descending stack grows in the direction of descending addresses, starting
from a high address and progressing to a lower one
 Most machines implement descending stacks as a default
Stack Implementation
Full/empty
 A misleading terminology, because is does not refer to whether the

stack is completely full or completely empty

 Rather, the SP can either point to the top item in the stack (full

method), or the next free space on the stack (an empty method)
 For the full method, when the stack is completely full, the SP

points to the upper limit of the stack. For the empty method, when
the stack is completely empty, the SP points to the base of the stack
The ARM architecture allows the system programmer to specify the
use of ascending or descending, empty or full stack operations
The x86 architecture uses a descending/empty convention
LITTLE- , BIG- ,AND BI-
ENDIAN
Byte Ordering
 The concept of endianness was first discussed in the literature by Cohen
[COHE81]
 Suppose we have the 32-bit hexadecimal value 12345678
 It is stored in a 32-bit word in byte-addressable memory at byte location
184
 The value consists of 4 bytes, with the least significant byte containing the
value 78
 The most significant byte containing the value 12.
 There are two obvious ways to store this value:
LITTLE- , BIG- ,AND BI-
ENDIAN
Big-Endian
 The mapping that stores the most significant byte

in the lowest numerical byte address; is known as

big endian and is equivalent to the left-to-right
order of writing in Western culture languages
Little-Endian
 The mapping that stores the least significant byte in

the lowest numerical byte address;is known as little

endian
LITTLE- , BIG- ,AND BI-
ENDIAN
 Some machines, such as the Intel 80x86, x86, are
little-endian machines
 IBM System 370/390, the Motorola 6800, Sun
SPARC, and most RISC machines, are big endian
 The PowerPC is a bi-endian processor that supports
both big-endian and little-endian modes
Addressing Modes
 The address field or fields in a typical instruction
format are relatively small
 We want to reference a large range of locations in
main memory or, for some systems, virtual
memory
 To achieve this objective, a variety of addressing
techniques has been employed
Addressing Modes
 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement (Indexed)
 Stack
Notations
(X) = contents of memory location X or register X
EA = actual (effective) address of the location
containing the referenced operand
R = contents of an address field in the instruction that
refers to a register
A = contents of an address field in the instruction
Immediate Addressing
 Operand is part of instruction
 Operand = address field
 e.g. ADD 5
 Add 5 to contents of accumulator
 5 is operand
 No memory reference to fetch data
 Fast
 Limited range
Immediate Addressing Diagram

Instruction

Opcode Operand
Direct Addressing
 Address field contains address of operand
 Effective address (EA) = address field (A)
 e.g. ADD A
 Add contents of cell A to accumulator
 Look in memory at address A for operand
 Single memory reference to access data
 No additional calculations to work out effective
address
 Limited address space
Direct Addressing Diagram

Instruction

Opcode Address A
Memory

Operand
Indirect Addressing (1)
 Memory cell pointed to by address field contains
the address of (pointer to) the operand
 EA = (A)
 Look in A, find address (A) and look there for operand
 e.g. ADD (A)
 Add contents of cell pointed to by contents of A to
accumulator
Indirect Addressing (2)
 Large address space
 May be nested, multilevel, cascaded
 e.g. EA = (((A)))
 Draw the diagram yourself
 Multiple memory accesses to find operand
 Hence slower
Indirect Addressing Diagram
Instruction

Opcode Address A
Memory

Pointer to operand

Operand
Register Addressing (1)
 Operand is held in register named in address filed
 EA = R
 Limited number of registers
 Very small address field needed
 Shorter instructions
 Faster instruction fetch
Register Addressing (2)
 No memory access
 Very fast execution
 Very limited address space
 Multiple registers helps performance
 Requires good assembly programming or compiler
writing
Register Addressing Diagram

Instruction

Opcode Register Address R

Registers

Operand
Register Indirect Addressing
 EA = (R)
 Operand is in memory cell pointed to by contents
of register R
 Large address space
 One fewer memory access than indirect addressing
Register Indirect Addressing Diagram

Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

 Displacement Addressing
 A very powerful mode of addressing combines the capabilities of
direct addressing and register indirect addressing
 Displacement addressing requires that the instruction have two
address fields, at least one of which is explicit
 The value contained in one address field (value = A) is used directly
 The other address field refers to a register whose contents are added
to A to produce the effective address.

Three of the most common uses of displacement addressing:

 Relative addressing

 Base-register addressing

 Indexing
Displacement Addressing
 EA = A + (R)
 Address field hold two values
 A = base value
 R = register that holds displacement
 or vice versa
Displacement Addressing Diagram

Instruction

Opcode Register R Address A

Memory

Registers

Pointer to Operand + Operand

 Relative Addressing
 For relative addressing, also called PC-relative addressing,
the implicitly referenced register is the program counter (PC)
 The next instruction address is added to the address field to
produce the EA.
 Typically, the address field is treated as a twos complement
number for this operation.
 Thus, the effective address is a displacement relative to the
address of the instruction.
 If most memory references are relatively near to the
instruction being executed, then the use of relative
addressing saves address bits in the instruction.
Relative Addressing
 A version of displacement addressing
 R = Program counter, PC
 EA = A + (PC)
 i.e. get operand from A cells from current location
pointed to by PC
Base-Register Addressing
 The referenced register contains a main memory
address, and the address field contains a
displacement from that address
 The register reference may be explicit or implicit.
Base-Register Addressing
 A holds displacement
 R holds pointer to base address
 R may be explicit or implicit
 convenient means of implementing segmentation
 e.g. segment registers in 80x86
 Indexing
 The address field references a main memory address, and the
referenced register contains a positive displacement from that
address
 Just the opposite of the interpretation for base-register
addressing
 Because the address field is considered to be a memory address
in indexing, it generally contains more bits than an address field
in a comparable base-register instruction
 The method of calculating the EA is the same for both base-
register addressing and indexing
 In both cases the register reference is sometimes explicit and
sometimes implicit (for different processor types).
Indexing: Example
 Indexing provides an efficient mechanism for performing
iterative operations
 Consider a list of numbers stored starting at location A.
Suppose that we would like to add 1 to each element on the
list. We need to fetch each value, add 1 to it, and store it
back. The sequence of effective addresses that we need is
A,A+1, A+2 . . ., up to the last location on the list
 With indexing, this is easily done. The value A is stored in
the instruction’s address field, and the index register is
initialized to 0. After each operation, the index register is
incremented by 1.
Indexing
 Autoindexing:
Because index registers are commonly used for such
iterative tasks, it is typical that there is a need to
increment or decrement the index register after each
reference to it. Because this is a common operation,
some systems will automatically do this as part of the
same instruction cycle. This is known as autoindexing.
 Autoindexing using increment can be depicted as follows

EA = A + (R)
(R) <--- (R) + 1
Indexing
 A = base
 R = displacement
 EA = A + R
 Good for accessing arrays
 EA = A + R
 R++
 Indexing
 Postindex
If indexing is performed after the indirection, it is termed
postindexing:
EA = (A) + (R)

 Preindex
If indexing is performed before the indirection, it is termed
preindexing:
EA = (A+(R))

 (Draw the diagrams)

Stack Addressing
 The stack mode of addressing is a form of implied
addressing. The machine instructions need not
include a memory reference but implicitly operate
on the top of the stack.
 Operand is on top of stack
 e.g.
 ADD Pop top two items from stack and
add
x86 Addressing Modes
 Virtual or effective address is offset into segment
 Starting address plus offset gives linear address
 This goes through page translation if paging enabled
 12 addressing modes available
 Immediate
 Register operand
 Displacement
 Base
 Base with displacement
 Scaled index with displacement
 Base with index and displacement
 Base scaled index with displacement
 Relative
 x86 Addressing Modes
 x86 address translation mechanism produces an address, called a
virtual or effective address, that is an offset into a segment
 The sum of the starting address of the segment and the effective
address produces a linear address
 The x86 is equipped with a variety of addressing modes intended
to allow the efficient execution of high-level languages
x86 Addressing Modes
x86 Addressing Modes
ARM Addressing Modes
 Typically, a RISC machine, unlike a CISC
machine, uses a simple and relatively
straightforward set of addressing modes
 The ARM architecture departs somewhat from this
tradition by providing a relatively rich set of
addressing modes
 These modes are most conveniently classified with
respect to the type of instruction
 ARM Addressing Modes
 LOAD/STORE ADDRESSING
Load and store instructions are the only instructions
that reference memory. This is always done indirectly
through a base register plus offset. There are three
alternatives with respect to indexing:
 Offset
 Preindex
 Postindex
ARM Addressing Modes
ARM Addressing Modes
 ARM Addressing Modes
 DATA PROCESSING INSTRUCTION
ADDRESSING
Data processing instructions use either register
addressing of a mixture of register and immediate
addressing
 BRANCH INSTRUCTIONS

The only form of addressing for branch instructions is

immediate addressing
 ARM Addressing Modes
 LOAD/STORE MULTIPLE ADDRESSING
Load Multiple instructions load a subset (possibly all) of
the general-purpose registers from memory
Store Multiple instructions store a subset (possibly all) of
the general-purpose registers to memory
The list of registers for the load or store is specified in a
16-bit field in the instruction
Each bit corresponding to one of the 16 registers
Load and Store Multiple addressing modes produce a
sequential range of memory addresses