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11/21/21 Mit Manipal
11/21/21 Mit Manipal
– AT
– ATX/NLX
AT type SMPS
Front side power connector to SMPS
AT style SMPS provides DC output on two 6-pin
connectors(carries DC power to motherboard) and two 4-pin
connectors
Power good flag is set
Power Consume.
Regulation : The ability of a SMPS to maintain an output
voltage within specified limits under varying of input voltage.
Power Supply Characteristic
Ripple : Also called AC Ripple or Periodic and Random
Deviation(PARD) or simply Noise the Power Supply of course
produces DC outputs from AC input.
Load Regulation: Sometimes called voltage load regulation.
This specification refers to the ability of the power supply to
control the output voltage level
Line Regulation: The complement of load regulation, this
parameter describes the ability of the power supply to control
its output levels
Power Supply problems
Blackouts: it is complete loss of electric power where voltage and current
drop to 0,usually caused by physical interruption in the power line due to
accidental damage by a person or act of nature, loss of AC will invariably
shutdown the computer,loss of data, reduction productivity, corrupt file
structure and damage files.
Brownouts (Sag): The under voltage condition The high load items like air
conditioners, welding machine, motor etc draw to much current that the
AC voltage level drops.
power supply will fall out which resulting in intermittent system operation.
file may be lost or corrupted on the hard drive.
ATX/NLX type SMPS
Power Supply problems
Surge: small over voltage conditions that take place over relatively long
periods and regulate power to a desired level excess energy must be
switched (in SMPS).
Spikes: A spike is a large over voltage condition that occurs in the
milliseconds. high energy switches can cause spikes on the AC line. Example
equipment like drill machine, grinders, welding equipment etc. can produce
power spikes.
Symptoms Supply problems
1. Flickering Lights,
4. You suffer chronic or frequent hard drive failures or file access problems.
becomes corrupted.
7. The PC behaves erratically when other high-energy devices are turned on.
38
Outline (II)
RL vO = (vOiO)/(vgig) vg RL vO
vg
iO i g
vE vE -
- Av
Av vO/vg
Feedback loop Vref Feedback loop Vref
ig Q iO S
ig iO
vg RL vO
vg RL vO
vE -
Av vE -
PWM Av
Feedback loop Vref
Feedback loop Vref
Linear
Switching (provisional)
Features:
vO_avg
vO 100% efficiency
vg
Undesirable output voltage
waveform
t
11/21/21 MIT MANIPAL 41
Introducing the switching DC/DC conversion (I)
S vO
ig iO vO_avg
vg
vg RL vO t
The AC component must be
vE -
PWM Av removed!!
Feedback loop Vref
S
ig iO
S
ig iO
Filter
vg RL vO
vg RL vO
C filter
PWM Av -
C filter vE
Vg VO Feedback loop Vref
t
Basic switching DC/DC
It doesn’t work!!! converter (provisional)
11/21/21 MIT MANIPAL 42
Introducing the switching DC/DC conversion (II)
S iL
ig iO S
ig iO
Filter L
vg RL vO LC filter
vg RL vO
C
PWM Av -
vE LC filter
S iL
ig iO
+ L + vD VO
vD RL vO Vg
vg iD C
D - -
t
LC filter
Basic switching DC/DC converter
11/21/21 MIT MANIPAL 43
Introducing the switching DC/DC conversion (III)
iS iL
S iL iO
iO ig
ig
L
S + L C +
+ + vD vO
vD vO vg RL
vg iD RL iD D - -
D - C -
L & C designed for negligible output voltage ripple (we are designing a DC/DC
converter)
The study of the Discontinuous Conduction Mode (DCM) will done later
CCM DCM
iL
iL
t t
iS iL iL
ig iO iO
+ L C
S + L C + +
vD vO vD RL vO
vg RL -
iD D - -
LC filter
vD
vg vD vD_avg = vO
vO vg
t t
dT The AC component is
T d: “duty cycle” removed by the filter
ig L1 C1 iD D
+ -
iS iL2 R
+
Vg VO
L2 C2 -
S
The average voltage across an inductor is zero. Else, the net current
through the inductor always increases and, therefore, steady-state is not
achieved
The average current through a capacitor is zero. Else, the net voltage
across the capacitor always increases and, therefore, steady-state is not
achieved
+
L vL_avg = 0
Circuit in -
Vg
steady-state
C iC_avg = 0
Circuit in
L vL + t
- - -v2
Vg steady-state dT
C iC T Volt·second balance:
V1dT – V2(1-d)T = 0
vL_avg = 0 iC_avg = 0
iC
+ t
-
Same areas
11/21/21 MIT MANIPAL 49
Introducing another analysis method (V)
Any electrical circuit of small dimensions (compared with the
wavelength associated to the frequency variations) satisfies:
Kirchhoff’s current law (KCL) is not only satisfied for instantaneous current values, but
also for average current values
Kirchhoff’s voltage law (KVL) is not only satisfied for instantaneous voltage values, but
also for average voltage values
ig Input power:
iO
Pg = vgig_avg
Switching-mode +
vg RL vO Output power:
DC/DC converter -
PO = vOiO = vO2/RL
Power balance:
Therefore: vgig_avg = vO2/RL
Pg = PO
Step 1: Main waveforms. Remember that the output voltage remains constant
during a switching cycle if the converter has been properly designed
ig vS iS iL iO
+ -
Driving signal
iD + L C +
S vD vO
vg RL
- t
D -
iL
iL iO
t
S on, D L C +
vO iS
off vg RL
-
t
During dT
iL iO iD
t
S off, D L C +
RL vO dT
on -
T
During (1-d)T
11/21/21 MIT MANIPAL 52
Analysis for the Switch Closed iL iO
S on, D VL C +
RL vO
off vs -
Rearranging
During dT
The change in current while the switch is closed is
computed by modifying the preceding equation.
2
11/21/21 MIT MANIPAL 53
iL iO
S off, D L C +
RL vO
on -
During (1-d)T
iC_avg = 0 iD L iC +
Node1 vO
S RL
Volt·second balance: vg
D -
C
(vg - vO)dT - vO(1-d)T = 0
Therefore: vO = d·vg (always vO < vg)
Driving signal
Step 3: Average KCL and KVL:
t
KCL applied to Node1 yields: iL
iL - i C - i O = 0 iL_avg
t
iL_avg - iC_avg - iO = 0 vL
vg-vO
Therefore: iL_avg = iO = vO/RL + t
ig vS iS iL iO Summary
+ -
iD + L C + Driving signal
S vD vO
vg RL
- t
D -
vD
vg
vO = d·vg (always vO < vg)
t
vSmax = vDmax = vg iL iO
iL_avg = iO = vo/RL t
iS
ig_avg = iS_avg = d·iO iL
t
iD_avg = iL_avg - iS_avg = (1-d)·iO
iD
iL = vO(1-d)T/L
t
iL_peak = iL_avg + iL/2 = iO + vO(1-d)T/(2L) dT
iS_peak = iD_peak = iL_peak T
11/21/21 MIT MANIPAL 61
11/21/21 MIT MANIPAL 62
11/21/21 MIT MANIPAL 63
1) A cuck converter has an input of 12V and its output of -18V supplying a
40W load. select the duety ratio. The switching frequency is 5 0kHz, the
inductor size such that the change in inductor current is no more than 10%
of the average inductor current, the output ripple voltage is no more than
1%. And ripple voltage C1 is no more than 5%.
ig + vL - iL - vD + iO Summary
L iC Driving signal
iS D iD +
+ RL vO t
vg S vS C -
- vD
vO
t
vO = vg/(1-d) (always vO > vg)
iL
vSmax = vDmax = vO
t
iL_avg = ig_avg = iO/(1-d) = vo/[RL(1-d)] iS
iL
iS_avg = d·iL_avg = d·vo/[RL(1-d)] t
iL + dT
S off, D on, C - -
vL RL
vO T
during (1-d)T L - + +
From Faraday’s law:
Discharging stage iL = vgdT/L
11/21/21 MIT MANIPAL 79
Steady-state analysis of the Buck-Boost converter in CCM (II)
iC_avg = 0 iL D iC
+ - -
S vO
Volt·second balance: vL C + RL +
vg L -
vgdT - vO(1-d)T = 0
Therefore: vO = vgd/(1-d)
Driving signal
Step 3: Average KCL and KVL:
t
KCL applied to Node1 yields: iD
iD_avg iL
iD - i C - i O = 0 t
iD_avg - iC_avg - iO = 0 vL
vg
Therefore: iD_avg = iL_avg(1-d) = iO = vO/RL t
ig i iD + vD - iO Summary
+ vS - S
iL Driving signal
+ D - -
S vO t
vL + RL +
vg L C
- vD
vO + v g
t
vO = vgd/(1-d) (both vO < vg and vO > vg)
iL
vSmax = vDmax = vO + vg
t
iD_avg = iO iL = vgdT/L iS
iL
t
iL_avg = iD_avg/(1-d) = iO/(1-d) = vo/[RL(1-d)]
iD
iS_avg = ig_avg = d·iL_avg = d·vo/[RL(1-d)] iO
L + +
S vO Complementary
vg C - RL
D - switches + inductor
Buck
S D
L d 1-d
D + + + +
vO vO
vg C - RL vg C - RL -
S - L
Boost
D +
- vO Voltage source
S
vg L C + RL -
L ig_avg iO
+ +
S vO
vg C - RL
D - +
RL vO
Buck vg -
ig iO 1:N
DC Transformer
L D + +
vO
vg S C - RL -
+
RL vO
vg -
1:N
DC Transformer
ig iS vS iO
+ -
iD + +
S vD RL vO
vg -
D -
DC/DC converter
4 A (avg) 2A
D vS_max = vD_max = 75 V
- -
S 50 V iS_avg = 4 A
25 V C + RL +
L
iD_avg = 2 A
100 W Buck-Boost, 100% efficiency iL_avg = 6 A
FOMVA_S = 300 VA
Higher electrical stress in the case of Buck-
Boost converter FOMVA_D = 150 VA
Therefore, lower actual efficiency
11/21/21 MIT MANIPAL 89
Comparing basic DC/DC converters (VI)
6.12 A (avg) L 5A
vS_max = vD_max = 60 V
1.12 A D + + iS_avg = 1.12 A
(avg) C - RL 60 V iD_avg = 5 A
50 V S -
iL_avg = 6.12 A
300 W Boost, 98% efficiency FOMVA_S = 67.2 VA
FOMVA_D = 300 VA
D
- -
S 60 V
C + RL +
20 - 200 V L vS_max = vD_max = 260 V
iS_avg_max = 20 A
300 W Buck-Boost, 75% efficiency
iD_avg_max = 5 A
Remember previous example: iL_avg = 25 A
FOMVA_S = 67.2 VA
FOMVA_S_max = 5200 VA
FOMVA_D = 300 VA
FOMVA_D = 1300 VA
L D + +
vg vO
S C - RL -
Boost
L idevice
S L
D MOSFET S1
Diode S2
L
S1
S2 vdevice
11/21/21 MIT MANIPAL 94
Synchronous rectification (II)
L
L S2 + +
S1 S1 vO
vg C - RL -
vO D
S2
Synchronous Buck
Q’ -
PWM Av
Q Vref
Feedback loop
ig iS vS iRC
+ -
iD + + +
S vD v
vg C - RL - O
D -
t t
11/21/21 MIT MANIPAL 96
Input current and current injected into the output RC cell (II)
ig iRC
ig iRC
L + +
S vO
vg C - RL
t D - t
Noisy Buck Low noise
ig iRC
ig L D + +
iRC
vO
vg S C - RL -
t t
Low noise Boost Noisy
ig iRC
ig D
-
+
vO
iRC
S -
C + RL
t vg L t
Noisy Buck-Boost Noisy
11/21/21 MIT MANIPAL 97
Input current and current injected into the output RC cell (III)
LF + L + +
S vO
vg CF - C - RL
D -
Filter Buck
ig iRC
L D LF
+ + +
R vO
vg S CF - C - L -
Boost Filter
ig iRC
LF D LF
+ - - -
CF S CF vO
vg - + C + RL +
L
Filter
Buck-Boost Filter
11/21/21 MIT MANIPAL 98
Four-order converters (converters with integrated filters)
ig L1 C1 iD
-
D
Same v /v as Buck-Boost
O g
+
iS vC1 iL2
+ RL Same stress as Buck-Boost
vg L2 C2 -
vO v =v C1 g
S
Filtered input
SEPIC ig L1 C1 iL2 L2
-
Same vO/vg as Buck-Boost iS
+
vC1 iD RL
-
Same stress as Buck-Boost vg vO
D C2 +
v =v +v
C1 g O S
+ Driving signal
S RL vO t
vg D -
dT
DC/DC converter
T
= iO/(1-d)
11/21/21 MIT MANIPAL 100
DC/DC converters operating in DCM (II)
RL_1
iL
iL_avg
Decreasing load
t
Operation in CCM
RL_2 > RL_1
iL
iL_avg
t
RL_crit > RL_2 Boundary between CCM
iL iL_avg
and DCM
t
It corresponds to RL = R L_crit
11/21/21 MIT MANIPAL 101
DC/DC converters operating in DCM (III)
What happens when the load decreases below the critical value?
CCM w. SR
t CCM operation is possible with
synchronous rectifier with a proper
driving signal (synchronous rectifier with
signal almost complementary to the main
RL_3 > RL_crit
iL iL_avg transistor)
t
DCM w. diode
Remember:
iL_avg = iO (Buck) or iL_avg = iO/(1-d) (Boost and Buck-Boost)
t
iL
After decreasing the
switching frequency
t
iL After decreasing the
load (increasing the
load resistance)
t
Vo D2
Vd 0.25I o
D2
I LB ,max
1 T i L, pp Vo (1 D )
Q
2 2 2 8 f sw2 L
Q Vo (1 D)
vo , pp
C 8 f sw2 LC
Vo (1 D ) (5)(1 0.5)
iL , pp 6
0.38 A
f sw L ( 2 10 )(33 10 )
5
Q Vo (1 D ) (5)(1 0.5)
vo , pp 6 6
24 mV
C 2
8 f sw LC 8( 2 10 ) (33 10 )(10 10 )
5 2
N=d 1 d
N= N=
1-d 1-d
2
M= d
4d2 M=
4k 1+ 1+
1+ 1+ 2 k k
d M=
2
kcrit = (1-d)2
kcrit = (1-d) kcrit = d(1-d)2
kcrit_max = 1
kcrit_max = 1 kcrit_max = 4/27
k = 2L/(RT)
11/21/21 MIT MANIPAL 119
DC/DC converters operating in DCM (X)
CCM versus DCM
Driving signal Driving signal
t
vD t vD
dT t dT t
T T
When the switch is closed, the diode is off. The voltage across L for the
1
interval DT is
When the switch is open, the diode is on. Kirchhoff’s voltage law around the
outermost path gives
Vs
for the interval (1 D)T. Since the average voltage across an inductor is zero for
periodic operation,
Power supplied by the dc source is voltage times the average current, and the
source current is the same as the current in L . 1
Solving for average inductor current, which is also the average source
current,
For L , the average current is determined from Kirchhoff’s current law at the
2
Using Kirchhoff’s voltage law around the path of the closed switch, C , and L
1 2
The output stage consisting of the diode, C , and the load resistor is the same as in
2
The resistances in the inductors and the capacitors can also have large
effects on the converter efficiency and output ripple. Inductors with lower
series resistance allow less energy to be dissipated as heat, resulting in
greater efficiency (a larger portion of the input power being transferred to
the load).
Capacitors with low equivalent series resistance (ESR) should also be used
for C1 and C2 to minimize ripple and prevent heat build-up, especially in C1
where the current is changing direction frequently.
•Since the SEPIC converter transfers all its energy via the series capacitor,
a capacitor with high capacitance and current handling capability is
required.
•The fourth-order nature of the converter also makes the SEPIC converter
difficult to control, making it only suitable for very slow varying
applications.
Solar PV Array Fed Water Pumping System Using SEPIC Converter Based
BLDC Motor Drive
Lm1 Lm1
n1:n2 n1:n2 n1:n2
Lm1
n1:n2
In a place where the
average voltage is zero
ig iO
vS
+ - + +
vD RL vO
vg D - -
S
DC/DC converter
L + +
S vO
vg C - RL -
D
S on S off D2
L + +
S RL vO
vg Lm1 C - -
D1
n1:n2
It does not work!!
11/21/21 MIT MANIPAL 141
Achieving a Buck converter with galvanic isolation (II)
n1:n1:n2 D2
L + +
D1 RL vO Standard design:
C - -
Lm1
vextra = vg
vg n3 = n 1
D3 Final implementation: the
S Forward converter
S on S off
D - -
S RL vO
vg L C + +
n1:n2
Other currents and voltages of interest while the switch is open are
Volt·second balance:
D3 Inductor magnetizing
vg S & D2 on, D1 stage
S & D2 off, D1
S & D3 off, im1
on, during dT
+
vL
vg Lm1
during (1-d)T D3 on, during d’T -
iL iO im1 Transformer
+ magnetizing stage
L C +
vO vg vL
RL Lm1 vO = dvgn2/n1
- -
Inductor demagnetizing Transformer reset vSmax = 2 vg
stage stage dmax = 0.5 (reset transformer)
11/21/21 MIT MANIPAL 154
When Switch is Closed
Vo = VsD= 5V
3 .6 7 A
1 .6 7 A
4s 10s t
-4 A
F ig .Q 1 C
Determine the output voltage; the average, maximum, and minimum inductor
currents; and the variation in voltage across each capacitor
1. Television
2. Aeronautics
3. Telecommunications
4. Converters and Inverters
5. Industrial Equipment
D - -
S RL vO
vg L C + +
n1:n2
Two-winding
inductor ig
+
n1:n2 D S on, D off, vL
during dT vg L1 -
+ +
L1 L2 RL vO
C - - Charging stage
iO
vg
+
C - -
S vLn2/n1 vO
RL
S off, D on, - L2 + +
during (1-d)T
Final implementation: the Discharging stage
Flyback converter
11/21/21 MIT MANIPAL 195
Achieving other converters with galvanic isolation (I)
L1 C1 n1:n2
L D RL + -
+ + D
vO vg L2 + RL
vg S C - - vO
Boost C2 -
S
SEPIC
It is not possible with
only one transistor!!
A H2 H(x)2
H(x)2
x
VP
PWM vd VPV
Ramp VV
generator vgs
(oscillator)
-
tC
+ + +
vd vgs TS
- - vd - VV
d=
VPV
- Logic
-
Av
circuitry +
+
+ + vgs
vd - Driver
-
- +
Reg V -
+
11/21/21 MIT MANIPAL 217
The control circuitry in DC/DC converters (III)
Ramp Power
generator
vg stage RL vO
(oscillator)
- L og ic
-
Av
c irc uitry +
+ Driver
+ + vgs
vd - Driver
- +
-
vd
PWM Av -
Reg V -
+
Output-voltage Vref
feedback loop
220
Inductors
Inductor symbols
221
FARADAY’S LAW OF
ELECTROMAGNETIC INDUCTION
If a conductor is moved through a The greater the number of flux lines cut per
magnetic field so that it cuts unit Time or the stronger the magnetic field
magnetic lines of flux, a voltage will strength, the greater will be the induced
be induced across the conductor voltage across the conductor.
Equation for voltage induced across a Increase the number of magnetic flux lines
coil if a coil of N turns is placed in the by increasing the speed with which the
region of a changing flux conductor passes through the field
222
Faraday’s law induced voltage equation
N = number of turns of the coil
&
223
Substituting µ = µr µo into Equation we get
224
Example 11.1
225
Example 11.1 cont’
226
11/21/21 MIT MANIPAL 227
11/21/21 MIT MANIPAL 228
11/21/21 MIT MANIPAL 229
11/21/21 MIT MANIPAL 230
11/21/21 MIT MANIPAL 231
11/21/21 MIT MANIPAL 232
Filter Inductor Design
KwAw =N.a
Gauge of wire
Cross section are of the wire can be calculated
KwAw J Kc = N.Im
Air gaop lg
L I m = N Ac B m
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 235
Introduction
Buck
Boost
Buck-Boost
Flyback, Forward, Push-Pull
Cuk
Sepic
Resonant Converters (SLR, PLR)
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 236 236
Basics
Permeability (μ)
Reluctance (S)
Low Cost
Low Losses
Temp. Linearity
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 237 237
Types of Cores
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 238 238
Principles of Inductor design
Number of Turns= N
Current flowing in the coil= I Amps
Mean magnetic length of core=lc
Mean length of Airgap= lg
Cross sectional area of core=Ac
Cross sectional area of air gap =Ag
lc lc
S S
o r AC o r Ac
NI ( SC S g ) To produce L henries of
inductance required number
of turns need to be
calculated
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 239 239
Types of Ferrite Cores
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 240 240
Cont…
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 241 241
Cont…
Parameters that needs to be calculated for the Inductor design
Window factor
Area product
Energy that can be handled by the Inductor
Number of turns required
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 242 242
Window factor/ Area Product
Assume the area of cross-section of the wire is ‘a’cm2.
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 243 243
Cont…
di d
eL N
dt dt
e LI m NAC Bm
Energy that can be handled by inductor is
1 2
E LI
2
1
E NAc Bm I m
2
Calculate Area Product (Ap)
2E
Ap AW Ac
K w Ac JBm
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 244 244
No. of Turns Required
Number of turns required are,
LI m
N
Ac Bm
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 245 245
Core Mean Core cross- Window area Area Product AL
length section (Aw*100mm2) (Ap*10^4
(mm) (Ac*100mm2) mm2)
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 246 246
Sunday, November 21, 2021 DEPT. OF ELECTRICAL & ELECTRONICS ENGG., MIT - MANIPAL 247 247
Small-signal average models for DC/DC converters in CCM
^
e(s)·d Leq Quantities with hats are
perturbations
1:N + Quantities in capitals are
^v ^ ^v steady-state values
g j·d C RL - O
“s” is Laplace variable
VO VO
Buck: e(s) = 2 j= Leq = L N=D
D RL
Leq VO L 1
Boost: e(s) = VO(1- s) j= Leq = N=
RL RL (1-D) 2
(1-D)2 1-D
Buck-Boost (VO<0) :
-VO DLeq -VO L -D
e(s) = 2 (1- s) j= Leq = N=
D RL RL(1-D) 2
(1-D)2 1-D
11/21/21 MIT MANIPAL 248