SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY

(An Autonomous Institution)

Department of Computer Science and Engineering

20CS001-Computer Organization and Architecture (COA)

Unit 3
Processor Design

Course Coordinator:

Ms.S.Hebziba Jeba Rani,

Assistant Professor,

Department of Computer Science and Engineering,

Sri Ramakrishna Institute of Technology

11/23/21 UCSC001 – Computer Organization and Architecture 1

 MIPS Instruction
• MIPS assembly language simply refers to the
assembly language of the MIPS processor.

• The term MIPS is an acronym for Microprocessor

without Interlocked Pipeline Stages.

• It is a Reduced-Instruction Set Architecture

developed by an organization called MIPS
Technologies.
11/23/21 UCSC001 – Computer Organization and Architecture 2
 A basic MIPS implementation

An implementation includes a subset of core MIPS instruction set.

• The memory reference instructions: Load word (lw) and Store

word (sw)

• The arithmetic and logic instructions: add, sub, AND, OR and

slt (slt-set if less than)

• The instructions branch equal (beq) and jump (j)

11/23/21 UCSC001 – Computer Organization and Architecture 3
 An overview of the implementation
• For every instruction, the first two steps are identical

• Send the Program Counter (PC) to the memory that contains the
code and fetch the instruction from that memory

• Read one or two registers, using fields of the instruction to select

the registers to read. For load word instruction, we need to read only
one register, but most other instructions require that we read two
registers

• After these two steps, the actions required to complete the instruction
depend on the instruction class

11/23/21 UCSC001 – Computer Organization and Architecture 4

 Implementation of the MIPS
• All instructions start by using the Program Counter (PC) to
supply the instruction address to the instruction memory

• After the instruction is fetched, the register operands used

by an instruction are specified by fields of that instruction.

• Once register operands have been fetched, they can be

operated on to computer memory address (for a load or
store) to compute an arithmetic result (for ALU
instruction) or a compare (for a branch)

11/23/21 UCSC001 – Computer Organization and Architecture 5

 Implementation of the MIPS - Contd
• If it is an A-L instruction, the result from ALU is written to a
register.

• If the operation is Load/Store, the ALU result is used as an

address to either store a value from the registers or load a
value from memory into the registers.

• Branch require the use of the ALU output to determine the

next instruction address which comes either from the ALU
(Where the PC and branch offset are summed) or from an
adder that increments the current PC by 4.

11/23/21 UCSC001 – Computer Organization and Architecture 6

 An abstract view of implementation of the MIPS
subset showing the major functional units and the
major connections

• The above figure shows the data movement

11/23/21 UCSC001 – Computer Organization and Architecture 7

 Implementation of the MIPS
• Value written into the PC can come from one of two adders.
Data written in register file can come from either the ALU or
the data memory

• Thus input to a particular unit can come from different

sources. (hence a logic element chooses from a ong the
multiple sources and steers one of those sources to its
destination)

• A multiplexer (also known as a data selector) is a device that

selects between several analog or digital input signals and
forwards the selected input to a single output line
11/23/21 UCSC001 – Computer Organization and Architecture 8
 The basic implementation of the MIPS subset,
including the necessary multiplexers and control
lines

• The above figure shows the data path where three Multiplexers and control
lines for functional units are added
11/23/21 UCSC001 – Computer Organization and Architecture 9
 Implementation of the MIPS
• Based on the type of instruction, the units are
controlled.

• For example during LOAD operation the data

memory is read and whereas during STORE
operation, the data memory is written

• During LOAD and ALU operations, the register

file is written
11/23/21 UCSC001 – Computer Organization and Architecture 10
 Logic Design Conventions
• Two types of logic elements: (data path
elements)
1. Combinational element
2. State element

• These two types of circuitry work together to

make up a processor datapath.

11/23/21 UCSC001 – Computer Organization and Architecture 11

 Combinational element
• A combinational logic circuit is one whose output solely
depends on its current inputs (elements that operate on data
values are called combinational)

• Elementary building blocks: Logic gates 

• Example: half adder, full adder, multiplexer, de-multiplexer

11/23/21 UCSC001 – Computer Organization and Architecture 12

 State Element (Sequential logic)
• Sequential logic is an element whose output depends upon
present and past inputs.
• Elementary building block: memory elements
• Example: Flip-flops, counters, registers

11/23/21 UCSC001 – Computer Organization and Architecture 13

 State Element - Contd
• Elements contain state if it contains internal
storage

• State element has at least two inputs and one

output.

• The required inputs are the data value to be

written into the element and the clock, which
determines when the data value is written
11/23/21 UCSC001 – Computer Organization and Architecture 14
 Data Path and Control Path
• Datapath element is the unit that is used to operate on or hold
data within a processor (for example, ALU, registers, and
internal buses

• Elements of Data path

– Combinational elements
– State (sequential) elements

• Control path element is the hardware that tells the datapath

what to do, in terms of switching, operation selection, data
movement between ALU components, timing, etc.

11/23/21 UCSC001 – Computer Organization and Architecture 15

 Clocking Methodology
• Clocking methodology defines when signals can be read and
when they can be written

• Edge triggered clocking methodology: values stored in

sequential logic element are updated only on a clock edge
(the output of the sequential circuit changes during the high
voltage period or low voltage period)

• In level triggering, the output of the sequential circuit

changes during transits from the high voltage to low voltage
or low voltage to high voltage.
11/23/21 UCSC001 – Computer Organization and Architecture 16
 Clocking Methodology

• Any collection of combinational circuit have its

input from a set of state elements and its outputs
are written into a set of state elements

• Inputs are values that were written in a previous clock

cycle, while the outputs are the values that can be
used in a following clock cycle

11/23/21 UCSC001 – Computer Organization and Architecture 17

 Clocking Methodology

• A block of combinational logic is surrounded by two state elements, which

operates in single clock cycle: all signals must propagate from state element 1,
through combinational logic and to state element 2 in the time of one clock
cycle. The time necessary for the signals to reach state element 2 defines the
length of clock cycle

11/23/21 UCSC001 – Computer Organization and Architecture 18

 Building a Datapath
• Major components required to execute each
class of MIPS instruction

1. A Memory unit
2. Program Counter (PC)
3. Adder

11/23/21 UCSC001 – Computer Organization and Architecture 19

• A memory unit is used to store the instructions of a program and supply
instructions given an address

• PC is a register that holds the address of the current instruction

• An adder is required to increment the PC to the address of next instruction

11/23/21 UCSC001 – Computer Organization and Architecture 20

 Data path used for fetching instructions
and incrementing the PC

• To execute any instruction, the instructions are fetched from memory and
to prepare for executing the next instruction, the PC is incremented so that
it points to next instruction 4 bytes later.

11/23/21 UCSC001 – Computer Organization and Architecture 21