IMPLEMENTATION OF

DIGITAL PHASE LOCK

LOOP

USING VHDL

Implementation of Phase Lock Loop using VHDL 1

 Group Members:
Krunal Nandu – 0823125
Sonali Desai – 0823142
Bhargav Shah – 0823144

Under the Guidance of:

Prof. (Mrs.) ANUDEEPA S. KHOLAPURE

Implementation of Phase Lock Loop using VHDL 2

 Contents
• Introduction to Phase Lock Loop
• Why FPGA(Field Programmable Gate Array)?
• MATLAB Modeling & Simulation Results
• VHDL – An Introduction
• System Generator Block – Code Conversion
Process
• Xilinx Synthesis
• Hardware Simulation Results
• Conclusion & Future Scope

Implementation of Phase Lock Loop using VHDL 3

 Introduction to PLL
(Phase Lock Loop)

Implementation of Phase Lock Loop using VHDL 4

 DPLL-Digital Phase Lock
Loop Block Diagram:

PFD : Phase / Frequency Detector

VCO: Voltage Controlled Oscillator
Implementation of Phase Lock Loop using VHDL 5
 APPLICATIONS OF
Phase Lock Loops:
• Clock Distribution
• Frequency Synthesizers
• AM Detection
• FM Detector
• Cell Phone Transceivers

Implementation of Phase Lock Loop using VHDL 6

 Clock Distribution:

Implementation of Phase Lock Loop using VHDL 7

 FREQUENCY
SYNTHESIZERS:

Implementation of Phase Lock Loop using VHDL 8

 AM DETECTION:

Implementation of Phase Lock Loop using VHDL 9

 FM TRANSMITTER:

Implementation of Phase Lock Loop using VHDL 10

 FM DETECTOR:

Implementation of Phase Lock Loop using VHDL 11

 Why FPGA
(Field Programmable Gate
Array)?

Implementation of Phase Lock Loop using VHDL 12

 Need of FPGA:
COMPARISON OF LARGE SCALE INTEGRATED
CIRCUITS

Implementation of Phase Lock Loop using VHDL 13

 FPGA Architecture:

Implementation of Phase Lock Loop using VHDL 14

FPGA vs. Microcontrollers:
• Microcontrollers are based on CPU architecture. As all CPUs,
they execute instructions in a sequential manner.
• FPGAs are programmable logic and run in a parallel fashion.
• Microcontrollers have on-chip peripherals that also execute in
parallel with their CPU. But they are still much less
configurable than programmable logic.

Implementation of Phase Lock Loop using VHDL 15

 Advantages of FPGA
• Time to Market
• Performance
• Cost
• Reliability
• Maintenance

Implementation of Phase Lock Loop using VHDL 16

 DPLL Block Diagram

Implementation of Phase Lock Loop using VHDL 17

 Phase Detection Circuit

Implementation of Phase Lock Loop using VHDL 18

 MATLAB Digital Phase Lock
Loop Model

Delay:
Latency = 5 (Z-5)

Implementation of Phase Lock Loop using VHDL 19

 Input Waveform

Input Waveform
Characteristics:

Amplitude = 1v
Period = 2sec

% Duty Cycle = 50

Phase delay = 0sec

Implementation of Phase Lock Loop using VHDL 20

 Input Delayed Waveform
Input Delayed
Waveform
Characteristics:

Phase Delay = 5sec

% Duty Cycle = 50

Period = 2sec

Amplitude = 1v

Implementation of Phase Lock Loop using VHDL 21

 Output Waveform

Implementation of Phase Lock Loop using VHDL 22

 Error Signal

Error Signal is low when there is a mismatch in phase of both inputs.

Implementation of Phase Lock Loop using VHDL 23
VHDL – An Introduction

Implementation of Phase Lock Loop using VHDL 24

 Introduction
• Hardware description languages (HDL)
o Language to describe hardware
o Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware
Description Language
o Developed by DOD from 1983
o IEEE Standard 1076-1987/1993/200x
o Based on the ADA language
• Verilog
o IEEE Standard 1364-1995/2001/2005
o Based on the C language
Implementation of Phase Lock Loop using VHDL 25
 Applications of Hardware
Description Language
• Model and document digital systems
o Different levels of abstraction
• Behavioral, structural, etc.
• Verify design
• Synthesize circuits
o Convert from higher abstraction levels to lower
abstraction levels

Implementation of Phase Lock Loop using VHDL 26

 Built-in Datatypes
• Scalar (single valued) signal types:
o bit
o boolean
o integer
o Examples:
• A: in bit;
• G: out boolean;
• K: out integer range -2**4 to 2**4-1;
• Aggregate (collection) signal types:
o bit_vector: array of bits representing binary numbers
o signed: array of bits representing signed binary numbers
o Examples:
• D: in bit_vector(0 to 7);
• E: in bit_vector(7 downto 0);
• M: in signed (4 downto 0);
--signed 5 bit_vector binary number

Implementation of Phase Lock Loop using VHDL 27

Input-Output specification of
circuit
 Example: my_ckt
 Inputs: A, B, C
 Outputs: X, Y
A  VHDL description:
X
B my_ckt entity my_ckt is
Y port (
S A: in bit;
B: in bit;
S: in bit;
X: out bit;

Y: out bit);
end my_ckt ;
Implementation of Phase Lock Loop using VHDL 28
 RTL Design Flow Chart

RTL : Register Transfer Level

Implementation of Phase Lock Loop using VHDL 29

 XiLiNX SysGen :
System Generator

Implementation of Phase Lock Loop using

30
VHDL
 SysGen Design
Flow Chart

Implementation of Phase Lock Loop using VHDL 31

 SysGen Toolbox in
SIMULINK

Implementation of Phase Lock Loop using VHDL 32

SysGen– Code Conversion

System Generator
Block Parameters:

Compilation = HDL Netlist

Synthesis Tool = XST

HD Language = VHDL

FPGA Clock Period = 100ns

Simulink System period = 1s

Implementation of Phase Lock Loop using VHDL 33

 Spartan3 XC3S400 FPGA Trainer Kit:

Implementation of Phase Lock Loop using VHDL 34

 XC3S400 Specifications

Implementation of Phase Lock Loop using VHDL 35

 XiLiNX Synthesis

Implementation of Phase Lock Loop using VHDL 36

 Xilinx Project Navigator
Window

Implementation of Phase Lock Loop using VHDL 37

Implementation of Phase Lock Loop using VHDL 38
 RTL Schematic of the
VHDL Code

Implementation of Phase Lock Loop using VHDL 39

 VHDL Design Summary
d_pll_cw Project Status Report

Project File: d_pll_cw.xise • Parser Errors: No Errors

Programming File
Module Name: d_pll_cw • Implementation State:
Generated
Target Device: xc3s400-5pq208 • Errors: No Errors

Product Version: ISE 12.3 • Warnings: 32 Warnings (29 new)

All Signals Completely

Design Goal: Balanced • Routing Results:
Routed

Xilinx Default
Design Strategy: • Timing Constraints: All Constraints Met
(unlocked)
Environment: System Settings • Final Timing Score: 0 (Timing Report)

Implementation of Phase Lock Loop using VHDL 40

 Conclusion & Future Scope
• The Digital PLL Model Using MATLAB & VHDL was
successfully implemented on the FPGA kit.

• The input waveform seen on the CRO is tracked by the Digital

PLL and it produces an output waveform with similar
frequency characteristics.

• Although some amount of jitter is visible in the output

waveform, we can further refine the same using high precision
function generators and oscilloscopes.

Implementation of Phase Lock Loop using VHDL 41

The work of design, simulation and layout is challenging and
interesting. We learned a lot in this process, not only the
knowledge about VHDL, but also the importance of teamwork.
We felt excited when the simulation results are the same as what
we expected, when our design passed the Synthesis process and
especially when the programming window showed
“PROGRAMMING SUCCEEDED”.

Implementation of Phase Lock Loop using VHDL 42

 Observation Table
Sr. No. Voltage Input Signal Frequency Output Signal
Frequency

1
3V 100 Khz 100 Khz
2
3V 500 Khz 500 Khz
3
3V 1 Mhz 1 Mhz
4
3V 10 Mhz 10 Mhz
The lock in time of our model is very quick because of the simplicity of
the design. If we design a more complex PLL, the lock-in time may be
shorter.

Implementation of Phase Lock Loop using VHDL 43

 References
• [1] A. Demir, E. Liu, A. Sangiovanni-Vincentelli, and I. Vassiliou. Behavioral
simulation techniques for phase/delay locked systems. Proceedings of the IEEE Custom
Integrated Circuits Conference, pp. 453-456, May 1994.
• [2] Crawford, Advanced Phase-Lock Techniques using Simulink, Artech House, 2008.
• [3] Douglas Perry, VHDL by Example, 4th Ed. 2004.
• [4] F. Gardener, Phase Lock Techniques, Wiley Interscience publications, 1979.
• [5] Karris, Circuit Analysis with MATLAB Computing and Simulink/
SimPowerSystems Modeling, Orchard Publications 2009
• [6] R.E. Best, Phase-Locked Loops - Design, Simulation, and Applications, 4th Ed.,
McGraw-Hill, 1996.
• [7] Volnei A, Pedroni, MIT Press, Circuit Design With VHDL, 2004.
• [8] Xilinx Inc., "Spartan3E Starter Kit Board User Guide," UG230 vl.0, Mar. 2006.
• [9] Xilinx Inc., "Spartan3E FPGA Family: Complete Datasheet," DS312, May. 2006.

Implementation of Phase Lock Loop using VHDL 44

 THANK YOU!

Implementation of Phase Lock Loop using VHDL 45