Gate-Level

Minimization

Module 3: K map; 2,3,4 variables; NAND/NOR

Mano Chapter 3
Angelin Gladston, DCSE, Anna University
Outline

 Intro to Gate-Level Minimization

 The Map Method
 2-3-4-5 variable map methods
 Product-of-Sums Method
 Don’t care Conditions
 NAND and NOR Implementations
Gate-Level Minimization

 Finding an optimal gate-level implementation of Boolean

functions.
 Difficult to perform manually.
 Can use computer-based logic synthesis tool
 Exp: espresso logic minimization software

 Karnough Map (K-map) can be used for manual design of digital

circuits.
The Map Method

 The truth table representation of a function is unique.

 But, not the algebraic expression
 Several versions of an algebraic expression exist.
 Difficult to minimize algebraic functions manually.
 The map method is a simple proceure to minimize Boolean
functions.
 Pictorial form of a truth table.
 Called Karnough Map or K-Map.
 Two-Variable Map
 Four Minterms
 Two variables
 Four squares for four
minterms
 Figure b shows the
relationship between the
squares and the variables x
and y.
Two-Variable Map (Cont.)

 May only be useful to represent 16 Boolean functions.

 Exp: If m1=m2=m3=1 then
m1+m2+m3=x’y+xy’+xy=x+y (OR function)
 Three-Variable Map
 There are 8 minterms for 3 variables.
 So, there are 8 squares.
 Minterms are arranged not in a binary sequence, but in sequence similar to
the Gray code.
 Three-Variable Map (Cont.)
 The square for square m5 corresponds to row 1 and column 01 (101).
 Another look to m5 is m5=xy’z.
 When variables are 0, they are primed (ex: x’). Otherwise not primed (x).
 Three-Variable Map (Cont.)
 Two adjacent squares differs one variable (one primed other is
not).
 So, they can be minimized
 Ex: m5+m7=xy’z+xyz=xz(y’+y)=xz
 So, try to cover as many adjacent squares as possible by
the orders of two.
 1,2,4,8… squares that has the logical value1.
 Example 1
 Simplfy the Boolean function
F(x,y,z)=Σ(2,3,4,5)
F(x,y,z)=x’y+xy’
 Adjacent squares
 Some adjacent squares don’t touch each other.
 m0 is adjacent to m2 and m4 is adjacent to m6.
 m0+m2=x’y’z’+x’yz’=x’z’(y’+y)=x’z’
 m4+m6=xy’z’+xyz’=xz’(y’+y)=xz’
Example 2
 Simplfy the Boolean function
F(x,y,z)=Σ(3,4,6,7)
F(x,y,z)=yz+xz’
Example 3
 Simplfy the Boolean function
F(x,y,z)=Σ(0,2,4,5,6)
F(x,y,z)=z’+xy’
 Example 4
 F=A’C+A’B+AB’C+BC
 Express F as a sum of minterms.
 F(A,B,C)=Σ(1,2,3,5,7)

 Find the minimal sum-of-products expression

 F=C+A’B
Four-Variable Map

 16 minterms (and squares) for 4 variables.

 Example 5
 Simplfy F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13,14)
F(w,x,y,z)=y’+w’z’+xz’
 Example 6
 Simplfy F=A’B’C’+B’CD’+A’BCD’+AB’C’
F=B’D’+B’C’+A’CD”
Prime Implicant

 A product term obtained by combining the max. possible number

of adjacent squares.
 If a minterm is covered by only one prime implicant, that prime
implicant is said to be essential.
Example

 F(A,B,C,D)=Σ(0,2,3,5,7,8,9,10,11,13,15)
 Example
 F=BD+B’D’+CD+AD=BD+B’D’+CD+AB’
=BD+B’D’+B’C+AD=BD+B’D’+B’C+AB’
Five-Variable Map

 Not simple, is not usually used. 5 variables, 32 squares.

 Example 7
 Simplfy F(A,B,C,D,E)=Σ(0,2,4,6,9,13,21,23,25,29,31)
F=A’B’E’+BD’E’+ACE
Product-of-Sums Simplification

 Mark the empty squares by 0’s.

 Combine them (as we did for sum-of-products)
 We obtain F’ (complement of the function)
 Take the complement of F’ ((F’)’) to obtain F.
 Example 8
 Simplfy F(A,B,C,D)=Σ(0,1,2,5,8,9,10)
F=B’D’+B’C’+A’C’D
F’=AB+CD+BD’ => F=(A’+B’)(C’+D’)(B’+D)
Example 8 gate impl.

 Two different implementations of the same function.

Don’t Care Conditions

 In practice’ some combinations are not specified as 1’s

or 0’s.
 Four bit binary codes has six unused combinations.
 Functions having unspecified outputs are called
incompletely specified functions.
 We don’t care the unspecified minterms
 These minterms are called don’t-care conditions.
 They can be used for minimization.
 They are indicated as X’s in the map.
 They can be assumed as 1’s or 0’s to have best simplification.
Example 9

 Simplfy F(w,x,y,z)=Σ(1,3,7,11,15) having don’t conditions

d(w,x,y,z)= Σ(0,2,5)
NAND and NOR Implementation

 Generally used for circuit design

 Easier to fabricate.
 Basic gates
 Other functions can be generated from them.
 Rules have been developed to convert functions to NAND and NOR
only implementations.
NAND Circuits

 NAND gate is universal

 Any digital system can be implemented with it.
 AND, OR and NOT can be implemented with NANDs.
Two graphic symbols of NAND
Two-Level Implementation

 Have the function in sum-of-product form.

 Put bubbles (inverters) to have two different representations of
NAND gate
 Either AND-invert or Invert-OR
Example: F=AB+CD
 Example 10
 Implement F(x,y,z)=Σ(1,2,3,4,5,7) with only NAND gates.
 Multilevel NAND Circuits
 F=A(CD+B)+BC’
NOR Implementation

 Dual of NAND operation

Example: F=(A+B)(C+D)E
Example: F=(AB’+A’B)(C+D’)
Exclusive-Or (XOR) Function

 XOR
x  y  xy   x y
 1 if only x is one or if only y is 1
 XNOR ( x  y )  xy  xy
 1 if both inputs are 1 or both inputs are 0
 Some identities of XOR
x0  x
x  1  x'
x x  0
x  x'  1
x  y '  x' y  ( x  y )'
XOR Implementations
 Odd Funct’on
 N variable XOR function is odd function defined as
 The logical sum of the 2n/2 minterms whose binary numerical values have an odd number
of 1’s. If n=3, 4 minterms have odd number of 1’s.
Logic Diagram of odd and even
functions
Parity Generation

 A parity bit is an extra bit included with a binary message

 If number of 1’s is odd, parity bit is 1; else 0.
 The circuit that generates the parity bit in the transmitter is called
parity generator.
 Parity bit can be generated using XOR function.
3-Bit Parity Generator
Parity Checker

 Bits are transmitted to the destination with parity.

 The circuit that checks the parity in the receiver is called a parity
checker.
 Parity checker can be implmeneted with XOR gates.
3-Bit Parity Checker