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    This document discusses the design of a VLSI-based clock generator that can generate both analog and digital clocks. It covers different types of clock generators including analog, digital, and DLL-based clock generators. It discusses the major design challenges in implementing such a clock generator in VHDL such as operating frequency, power dissipation, and clock skew. It provides block diagrams of the proposed analog clock generator design including components like the phase detector, charge pump, loop filter, and voltage-controlled delay line. In conclusion, it presents this work on designing a VLSI-based clock generator and references papers on related clock generator designs.

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    This document discusses the design of a VLSI-based clock generator that can generate both analog and digital clocks. It covers different types of clock generators including analog, digital, and DLL-based clock generators. It discusses the major design challenges in implementing such a clock generator in VHDL such as operating frequency, power dissipation, and clock skew. It provides block diagrams of the proposed analog clock generator design including components like the phase detector, charge pump, loop filter, and voltage-controlled delay line. In conclusion, it presents this work on designing a VLSI-based clock generator and references papers on related clock generator designs.

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    16 views18 pages

    Vlsi Based Clock Generator (Analog, Digital

    Uploaded by

    lakshmi610
    This document discusses the design of a VLSI-based clock generator that can generate both analog and digital clocks. It covers different types of clock generators including analog, digital, and DLL-based clock generators. It discusses the major design challenges in implementing such a clock generator in VHDL such as operating frequency, power dissipation, and clock skew. It provides block diagrams of the proposed analog clock generator design including components like the phase detector, charge pump, loop filter, and voltage-controlled delay line. In conclusion, it presents this work on designing a VLSI-based clock generator and references papers on related clock generator designs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
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    of 18

    VLSI BASED CLOCK

    GENERATOR(ANALOG,DIGITAL)

    UNDER THE GUIDANCE OF

    PROF. M. KAMARAJU

    P.Krishna Priyanka(07481a0470)
    K.Lakshmi Prudhvi(07481a0447)
    Sk.Ahmed Alisha(07481a0403)
    Y.Naveen Chandra(07481a0465)
    CONTENTS
     clock generator
    Clock generator types
    Analog

    Digital

    DLL based clock generator


    Major design challenges
    VHDL Implementation

    Conclusion
    CLOCK GENERATOR
     A clock generator is a circuit that produces a timing signal for use
    in synchronizing a circuit's operation. The signal can range from a
    simple symmetrical square wave to more complex arrangements.
     Other such optional sections include frequency divider or
    clock multiplier sections
     Comparision with existing clock generator
     Advantages: why we have to generate internal clock ?
     Clock generator requirements
    DESIGNING TECHNOLOGY

    o VLSI Designing technologies


    1. Front-end
    2. Back-end
    o Importance of Front-end, Back-end designing
    CLOCK GENERATION TECHNIQUE

    o Clock generation mechanisms


    • PLL
    • DLL
    o Why we prefer DLL?
    o Design challenges compared to PLL
    CLOCK SKEW
     Clock skew is the difference in clock signal arrival time
    between two sequentially adjacent registers (blocks).
     Clock skew is due to the unbalanced of the data paths
    (i.e. different propagation delay).
    DESIGN CHALLENGES
     Operating frequency(up to Ghz)
     The proposed frequency multiplier possess the
    programmable function, and the output clock frequency
    is Ix, 2x and 4x of an input
     Power dissipation

     DLLs are practically considered suitable for clock


    multiplication applications,
    Block diagram of analog clock generator

    Voltage
    Charge pump
    Phase detector controlled
    and loop filter
    delay line

    Clock
    generation
    PHASE DETECTOR BLOCK DIAGRAM
    PHASE DETECTOR
     Importance of phase detector
     Operation

     Allowable range of frequencies.(21.875 MHz to 28.47


    MHz)
    PROPOSED PHASE DETECTOR
    CONCLUSION
    REFERENCES
     S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz. Adaptive bandwidth
    DLLs and PLLs using regulated supply CMOS bu_ers. In Proc. IEEE Symposium
    on VLSI Circuits, pages 124_127, June 2000.
     Maneatis, et al., "Low-Jitter Process-Independent DLL and PLL Based on Self-
    Biased Tech- niques," IEEE Journal of Solid-State Circuits, Vol. 31, No. 11,
    November 1996
     B.W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V.
    Tran, C. L. Portmann, D. Stark, Y.-F. Chan, T. H. Leen, and M. A. Horowitz, _A
    Portable Digital DLL for High-Speed CMOS Interface Circuits,_ IEEE J. Solid-
    State Circuits, vol. 34, pp. 632_644, May 1999.
     S. Liu, J. Lee and H. Tsao, "Low-power clock-deskew bu_er for high-speed
    digital circuits", IEEE Journal of Solid-State Circuits, SC-34, pp. 554-558, April
    1999.
    THANK YOU

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