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R P Jain Modern Digital Electronics, Fourth Edition Tata McGraw-Hill Education © 2009

PowerPoint Slides

Modern Digital Electronics

Fourth Edition
R P Jain

PROPRIETARY MATERIAL. © 2010 The McGraw-Hill Companies, Inc. All rights reserved. No part of this PowerPoint slide may be displayed, reproduced or distributed in any form or by
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External outputs
External Inputs

Excitation
Next State Memory Output
Logic Elements Logic

Clock

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A 1-BIT MEMORY CELL

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R P Jain Modern Digital Electronics, Fourth Edition Tata McGraw-Hill Education © 2009

CLOCKED S–R FLIP-FLOP

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R P Jain Modern Digital Electronics, Fourth Edition Tata McGraw-Hill Education © 2009

J-K FLIP-FLOP

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R P Jain Modern Digital Electronics, Fourth Edition Tata McGraw-Hill Education © 2009

The Master–Slave J–K FLIP-FLOP

M v

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D-TYPE FLIP-FLOP

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T-TYPE FLIP-FLOP

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EXCITATION TABLE OF FLIP-FLOP

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CLOCKED FLIP-FLOP DESIGN

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Conversion from One Type of FLIP-FLOP to Another Type

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EDGE-TRIGGERED FLIP-FLOPs

Set-up time (ts)

Hold time (th)

Propagation Delays

Clock Pulse Width

Preset and Clear Pulse Width

Maximum Clock Frequency

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Timing Parameters of TTL and CMOS FLIP-FLOPs

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APPLICATIONS OF FLIP-FLOPs

1. Bounce elimination switch,

2. Latch,
3. Registers,
4. Counters,
5. Memory, etc.

Bounce-Elimination Switch

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S
Q

A S

Q
R

(a) Latch

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1
S
0 t
0
1
R
0 t1 t2 t3 t
1
Q
0 t
1
Q
0 t

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Registers

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Counters

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Random-Access Memory

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