Electronic devices &

circuits

Lecture-2 UNIT-4

Field Effect Transistor

Dr. mohammed mahaboob basha
Associate Professor
Dept. of ECE
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JFET Biasing
 JFET Fixed Bias
VGG + IGRG + VGS = 0 Since GS is reverse biased, IG = 0
Since IG = 0 and Voltage drop across RG = 0
VGS = - VGG

January 2004 ENGI 242/ELEC 222 5

 DC Analysis for JFET Fixed Bias Network
We can find the value of drain current ID from the
relation given below as IDSS and VGS(off) (= – VP) are given
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in transistor data sheet.  VGS 
ID = IDSS  1 - 
 V P 
From output loop, Since VGS = - VGG
we can write as  VGG 
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ID = IDSS  1 - 
 V P 

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JFET Fixed Bias
JFET Fixed Bias Plotting Shockley’s Equation

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Location of Q - Point
JFET Fixed Bias

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Graphical Solution for JFET Fixed Bias
JFET Self Bias Configuration

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JFET Self Bias DC Equivalent Circuit

IG = 0

VRG = 0
Input Loop Output Loop
Transconductance Curve
 Self Bias Line

Superimposing this straight line

on the transfer curve, we get
Q- Point
JFET Self Bias Load Line
JFET Self Bias Transconductance Curve
Graphical Solution of JFET Self Bias
JFET Self Bias Effect on Variation of RS

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