DEPpart2 Cuong

©
R.Lauwereins
Imec 2001
Course contents
Digital
• Digital design
design
 Combinatorial circuits: without status
Combina-
torial
• Sequential circuits: with status
circuits
• FSMD design: hardwired processors
Sequential
circuits
• Language based HW design: VHDL
FSMD
design
VHDL
2/1
©
R.Lauwereins
Imec 2001
Design of Combinatorial Circuits
Digital
• Minimization of Boolean functions
design
• Technology mapping
Combina-
torial
• Correct timing behavior
circuits
• Basic RTL building blocks (Adder, ALU,
Sequential MUX, …)
circuits
FSMD
design
VHDL
2/2
©
R.Lauwereins
Imec 2001
Digital
design
 Karnaugh map
Combina-  Minimization with the Karnaugh map
torial
circuits  Don’t care conditions
 Quine-McCluskey
Sequential
circuits • Technology mapping
FSMD
design
VHDL MUX, …)
2/3
©
R.Lauwereins
Imec 2001
Digital
design
 Karnaugh map
torial
 Quine-McCluskey
Sequential
FSMD
design
VHDL MUX, …)
2/4
©
R.Lauwereins
Imec 2001
Karnaugh map
Digital
• Motivation:
design
 Assume: F=xy’z+xy’z’
Combina-
torial
 Cost = (fan-in)complete circuit = (2)+2(3+1)+(2+1) =
circuits 13
Sequential
 Delay
circuits
Assume: relative gate delay NAND or
FSMD NOR or NOT = 0.6 + fan-in * 0.4
design
Delay = (gate-delay)critical path = 1 +

VHDL
(1.8+1)
x y +z (1.4+1) = 6.2
F=xy’z+xy’z’
2/5
©
R.Lauwereins
Imec 2001
Karnaugh map
Digital
• Motivation:
design
F =xy’z+xy’z’
Combina- =xy’(z+z’)
torial
circuits =xy’
The value of z hence does not matter
Sequential
circuits  Cost = (fan-in)complete circuit = 1+2+1 = 4 i.o. 13
FSMD  Delay
design
Assume: relative gate delay NAND or
VHDL NOR or NOT = 0.6 + fan-in * 0.4
Delay = (gate-delay)critical path = 1 +
(1.4+1) = 3.4 i.o. 6.2
x y z
F
2/6
©
R.Lauwereins
Imec 2001
Karnaugh map
Digital
• Minimization via manipulation of Boolean
design
expressions is clumsy: no method exists
Combina- to select the theorems such that we are
torial
circuits sure to obtain the minimum cost
• Is it possible to see in the truth table
Sequential
circuits which input value does not matter?
FSMD
design
x y z F
We indeed see easily that the
VHDL 0 0 0 0 -
value of F equals 1 for x=1 and y=0
0 0 1 0 -
irrespective of the value of z
0 1 0 0 -
0 1 1 0 -
1 0 0 1 xy’z’ We however see this easily only
1 0 1 1 xy’z for z, since only for z the lines
1 1 0 0 - z=0 and z=1 for equal x and y
1 1 1 0 - are consecutive
2/7
©
R.Lauwereins
Imec 2001
Karnaugh map
Digital
• A Karnaugh map contains the same
design
information as a truth table (each square
Combina- is a minterm), but…
torial
circuits • neighboring squares differ only in the
Sequential
value of 1 variable!!
circuits x y
0 1 x 0 1
FSMD
design x’ x 0 x’y’ x’y
VHDL z 1 xy’ xy
y
yz
x 00 01 11 10 xy’ (z does not matter)
0 x’y’z’ x’y’z x’yz x’yz’ x’z (y does not matter)
xz’ (y does not matter)

x 1 xy’z’ xy’z xyz xyz’
2/8
©
R.Lauwereins
Imec 2001
Karnaugh map
Digital
design x y
0 1 x 0 1
Combina-
torial m0 m1 0 m0 m1
circuits
Sequential 1 m2 m3
circuits
FSMD
design z
VHDL
y
yz
x 00 01 11 10
0 0 1 3 2
x 1 4 5 7 6
2/9
©
R.Lauwereins
Imec 2001
Karnaugh map
Fill out from truth table x y z w
w F
F
Digital
design w 0 0 0 0
0 1
1
z 0 0 0 1
1 0
0
Combina- zw 0 0 1 0 0
0
torial xy 00 01 11 10 0 0 1 1 0
circuits 0
0 1 0 0 0
0
00 0
1 1
0 3
0 2
0
Sequential 0 1 0 1
1 1
1
circuits
0
0 1
1 1
1 0
0 0
0
01 4
0 5
1 7
1 6
0 0 1 1 1 1
FSMD 0 1 1 1 1
design y 1
1 0
0 0
0 0
0
0 1
1
1
11 12
0 13
1 15
1 14
0 1
1 0
0 0
0 1
1
1 0
0
0
VHDL
x 1
1 0
0 1
1 0
0
0 1
1
1
1
1 0
0 1
1 1
1
1 0
0
0
10 8
1 9
0 11
0 10
1
1
1 1
1 0
0 0
0
0 0
0
0
1
1 1
1 0
0 1
1
1 1
1
1
1
1 1
1 1
1 0
0
0 0
0
0
1
1 1
1 1
1 1
1
1 1
1
1
2/10
©
R.Lauwereins
Imec 2001
Karnaugh map
Minimize
Digital F=x’y’z’w’+x’yz’w+x’yzw+xy’z’w’+xy’zw’+xyz’w+xyzw
design
Combina-
torial
circuits w
z
Sequential zw
circuits xy 00 01 11 10
FSMD 00 1 0 0 0
design
F= yw
VHDL 01 0 1 1 0
+xy’w’
y
11 0 1 1 0 +y’z’w’
x
10 1 0 0 1
2/11
©
R.Lauwereins
Imec 2001
Karnaugh map
Implement
Digital F=x’y’z’w’+x’yz’w+x’yzw+xy’z’w’+xy’zw’+xyz’w+xyzw
design
x y z w
Combina- Cost = 4*(1) + 7*(4+1) +
torial 1*(7+1)
circuits
= 47
Sequential
Delay = 1 + (2.2+1) + (3.4+1)
circuits = 8.6
FSMD
design
VHDL F
2/12
©
R.Lauwereins
Imec 2001
Karnaugh map
Implement
Digital F=yw+xy’w’+y’z’w’
design
x y z w
Combina-
torial
circuits
Sequential F
circuits
FSMD
design
Cost = 3*(1) + {1*(2+1)+2*(3+1)}

VHDL
+ 1*(3+1)
= 18 i.p.v. 47
Delay = 1 + (1.8+1) + (1.8+1)
= 6.6 i.p.v. 8.6
2/13
©
R.Lauwereins
Imec 2001
Karnaugh map
v
Digital
design w w
z z
Combina-
torial
zw
circuits 00 01 11 10 10 11 01 00
xy xy
Sequential
00 0 1 3 2 18 19 17 16 00
circuits
01 4 5 7 6 22 23 21 20 01
FSMD y y
design
11 12 13 15 14 30 31 29 28 11
x x
VHDL
10 8 9 11 10 26 27 25 24 10
F(v,x,y,z,w)
Differs from course book
2/14
©
R.Lauwereins
Imec 2001
Karnaugh map
v
Differs from course book
w w
Digital
design z z
zw
00 01 11 10 10 11 01 00
Combina-
torial
xy xy
circuits 00 0 1 3 2 18 19 17 16 00
Sequential 01 4 5 7 6 22 23 21 20 01
circuits
y
FSMD y 11 12 13 15 14 30 31 29 28 11
design x x
10 8 9 11 10 26 27 25 24 10
VHDL
F=(u,v,x,y,z,w)
10 40 41 43 42 58 59 57 56 10
x x
11 44 45 47 46 62 63 61 60 11
y y u
01 36 37 39 38 54 55 53 52 01
00 32 33 35 34 50 51 49 48 00
2/15
©
R.Lauwereins
Imec 2001
Digital
design
 Karnaugh map
Combina-  Minimization with the Karnaugh map
torial
 Quine-McCluskey
Sequential
FSMD
design
VHDL MUX, …)
2/16
Minimization with the Karnaugh
©
R.Lauwereins
Imec 2001
map
Digital
Truth table or
design canonical form
Combina-
torial
circuits
Create the Karnaugh map
Sequential
circuits
FSMD Determine all prime implicants

design
VHDL
Determine all essential

prime implicants
Search for minimal coverage
2/17
©
R.Lauwereins
Imec 2001
map
Digital
design
F=x’y’z’+wz+xyz+w’y Step 1: Create Karnaugh map
Combina-
torial
circuits z
y
Sequential
circuits
1 1 1
FSMD
design
1 1
x
1 1
VHDL w
1 1 1
Rule:
- Take product term per product
term and indicate where in the
Karnaugh map it equals 1
2/18
©
R.Lauwereins
Imec 2001
map
Digital
design
Step 2: Determine all prime implicants
Combina-
torial
circuits z w’x’z’
y x’y’z’
Sequential
circuits w’y
1 1 1 yz
FSMD
1 1 wz
design
x wx’y’
1 1
VHDL w
1 1 1
Rule:
- Analyze each 1-minterm
- Determine the largest sub-cube(s)
that contain(s) the minterm and
add them to the list of prime
implicants (without adding an
2/19 already listed sub-cube)
©
R.Lauwereins
Imec 2001
map
Digital
design
Step 3: Determine all essential prime implicants
Combina-
torial
circuits z w’x’z’
y x’y’z’
Sequential
circuits w’y
1 1 1 yz
FSMD
1 1 wz
design
x wx’y’
1 1
VHDL w
1 1 1
Rule:
- Search for 1-minterms that are
only contained in 1 prime implicant
- Indicate this prime implicant as
2/20 essential
©
R.Lauwereins
Imec 2001
map
Step 4: Search minimal coverage
Digital
design
z w’x’z’ 1
Combina- y x’y’z’ 2
torial
circuits w’y
1 1 1 yz 0
Sequential
1 1 wz
circuits
x wx’y’ 1
1 1
FSMD
design
w Fmin=x’y’z’+w’y+wz
1 1 1
VHDL Rule:
- Goal: search for the smallest set of (as big as possible)
prime implicants that contain all 1-minterms
- Take all essential prime implicants as initial list
- Repeatedly add a prime implicant to the list that contains
the largest number of not yet covered 1-minterms. When
there are two that contain the same number of not yet
covered 1-minterms, make a random choice.
- Such a strategy is known as Greedy strategy: at each decision point,
take the best choice without looking to future implications
2/21 - This does not always lead to a global optimum
©
R.Lauwereins
Imec 2001
map
• Original: • Minimal
Digital
design F=x’y’z’+w’y+xyz+wz Fmin=x’y’z’+w’y+wz
Combina- wxyz wxyz

torial
circuits
Sequential
circuits
FSMD
design
VHDL
Cost=4*1+2*(3+1)+2*(2+1) Cost =4*1+1*(3+1)+2*(2+1)

+1*(4+1)=23 +1*(3+1)=18
=22% cheaper
Delay =(1)+(.6+3*.4+1) Delay =(1)+(.6+3*.4+1)
+(.6+4*.4+1)=7 +(.6+3*.4+1)=6.6
2/22 =6% faster
©
R.Lauwereins
Imec 2001
map
Digital
• Example 2: F(v,w,x,y,z)
design
v w x y z F v w x y z F
Combina- 0 0 0 0 0 0 1 0 0 0 0 0
torial
circuits
0 0 0 0 1 0 1 0 0 0 1 0
0 0 0 1 0 0 1 0 0 1 0 0
Sequential 0 0 0 1 1 0 1 0 0 1 1 0
circuits
0 0 1 0 0 0 1 0 1 0 0 0
0 0 1 0 1 0 1 0 1 0 1 1
FSMD
design 0 0 1 1 0 1 1 0 1 1 0 0
0 0 1 1 1 1 1 0 1 1 1 1
VHDL
0 1 0 0 0 0 1 1 0 0 0 0
0 1 0 0 1 0 1 1 0 0 1 1
0 1 0 1 0 1 1 1 0 1 0 0
0 1 0 1 1 1 1 1 0 1 1 1
0 1 1 0 0 0 1 1 1 0 0 0
0 1 1 0 1 0 1 1 1 0 1 1
0 1 1 1 0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 1 1 1 1 1
2/23
©
R.Lauwereins
Imec 2001
map
Digital
• Realisation as sum of 1-minterms:
F=(6,7,10,11,14,15,21,23,25,27,29,31)
design
Combina- v
torial w
circuits x
y
z
Sequential
circuits
FSMD
design
VHDL
Cost=(5*1)+(12*(5+1))+(1*(12+1))=90
Delay=(.6+1*.4)+(.6+5*.4+1)+(.6+12*.4+1)=11
2/24
©
R.Lauwereins
Imec 2001
map
Digital
• Minimisation
design
Step 1: Create Karnaugh map
Combina-
torial
circuits v
z z
Sequential
circuits y
FSMD 0 0 0 0 0 0 0 0
design
0 0 1 1 0 1 1 0
VHDL x
0 0 1 1 0 1 1 0
w
0 0 1 1 0 1 1 0
2/25
©
R.Lauwereins
Imec 2001
map
Digital
• Minimisation
design
Step 2: determine all prime implicants
Combina-
torial
circuits v
z z
Sequential
circuits y
FSMD 0 0 0 0 0 0 0 0
design
0 0 1 1 0 1 1 0
VHDL x
0 0 1 1 0 1 1 0
w
0 0 1 1 0 1 1 0
2/26
©
R.Lauwereins
Imec 2001
map
Digital
• Minimisation
design
Step 3: Determine all essential prime
Combina- implicants
torial
circuits v
z z
Sequential
circuits y
FSMD 0 0 0 0 0 0 0 0
design
0 0 1 1 0 1 1 0
VHDL x
0 0 1 1 0 1 1 0
w
0 0 1 1 0 1 1 0
Is already the minimum coverage
F1min2=v’xy+v’wy+vxz+vwz
2/27
©
R.Lauwereins
Imec 2001
map
Digital
• Realisation of F1min2=v’xy+v’wy+vxz+vwz
design
v
w
Combina- x
torial y
circuits
z
Sequential
circuits
FSMD
design
VHDL
Cost=1+(4*(3+1))+(1*(4+1))=22 (76% cheaper)

Delay=(.6+1*.4)+(.6+3*.4+1)+(.6+4*.4+1)=7 (34% faster)
2/28
©
R.Lauwereins
Imec 2001
map
Digital
• Realisation in more than two layers
design
F =v’xy+v’wy+vxz+vwz
Combina- =v’y(x+w)+vz(x+w)
torial
circuits =(x+w)(v’y+vz)
Sequential
circuits
v Cost =(1*1)+(5*(2+1))=16
w
FSMD x (82% cheaper)
design y
z Delay =(.6+1*.4)+(.6+2*.4+1)
+(.6+2*.4+1)+(.6+2*.4+1)
VHDL
=8.2 (25% faster)
2/29
©
R.Lauwereins
Imec 2001
map
Digital
• Dual minimisation
design
Step 1: Create the Karnaugh map
Combina-
torial
circuits v
z z
Sequential
circuits y
FSMD 0 0 0 0 0 0 0 0
design
0 0 1 1 0 1 1 0
VHDL x
0 0 1 1 0 1 1 0
w
0 0 1 1 0 1 1 0
2/30
©
R.Lauwereins
Imec 2001
map
Digital
design
Step 2: Determine all prime implicants
Combina-
torial
circuits v
z z
Sequential
circuits y
FSMD 0 0 0 0 0 0 0 0
design
0 0 1 1 0 1 1 0
VHDL x
0 0 1 1 0 1 1 0
w
0 0 1 1 0 1 1 0
2/31
©
R.Lauwereins
Imec 2001
map
Digital
design
Step 3: Determine all essential prime
Combina- implicants
torial
circuits v
z z
Sequential
circuits y
FSMD 0 0 0 0 0 0 0 0
design
0 0 1 1 0 1 1 0
VHDL x
0 0 1 1 0 1 1 0
w
0 0 1 1 0 1 1 0
Is already the minimum coverage

F0min2=(v+y)(w+x)(v’+z)
2/32
©
R.Lauwereins
Imec 2001
map
Digital
• Realisation of F0min2=(v+y)(w+x)(v’+z)
design
v
w
Combina- x
torial y
circuits
z
Sequential
circuits
FSMD
design
VHDL
Cost=(1*1)+(3*(2+1))+(1*(3+1))=14 (84% cheaper)

Delay=(.6+1*.4)+(.6+2*.4+1)+(.6+3*.4+1)=6.2 (44% faster)
2/33
©
R.Lauwereins
Imec 2001
map
Digital
• Summary
design
Realisation Cost Rel. cost Delay Rel. delay

Combina-
torial Sum of 1-minterms 90 100% 11 100%
circuits
Minimal AND-OR 22 24% 7 64%
Sequential
3-layers 16 18% 8.2 75%
circuits Minimal OR-AND 14 16% 6.2 56%
Area/time trade-off
FSMD
design
VHDL We’ll see that, depending on the technology mapping,

we will eventually obtain for an ASIC realisation:
OR-AND-INV
Cost = 11 (Rel. cost=12%)
Delay = 4 (Rel. delay=36%)
NOR
Cost = 10 (Rel. cost=11%)
Delay = 4.2 (Rel. delay=38%)
2/34
©
R.Lauwereins
Imec 2001
Digital
design
 Karnaugh map
torial
circuits  Don’t care conditions
 Quine-McCluskey
Sequential
FSMD
design
VHDL MUX, …)
2/35
©
R.Lauwereins
Imec 2001
Don’t care conditions
Digital
• Incompletely specified Boolean function
design
x y z w a b c d e f g BCD7-segment
Combina- 0 0 0 0 1 1 1 1 1 1 0
torial
circuits
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1 a
Sequential 0 0 1 1 1 1 1 1 0 0 1
circuits
0 1 0 0 0 1 1 0 0 1 1 f b
g
0 1 0 1 1 0 1 1 0 1 1
FSMD
design 0 1 1 0 1 0 1 1 1 1 1
e c
0 1 1 1 1 1 1 0 0 0 0
VHDL
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1 d
1 0 1 0 x x x x x x x
1 0 1 1 x x x x x x x
1 1 0 0 x x x x x x x
1 1 0 1 x x x x x x x
1 1 1 0 x x x x x x x
1 1 1 1 x x x x x x x
2/36
©
R.Lauwereins
Imec 2001
Digital
• Step 1: Create Karnaugh maps
design
w w w w
Combina- a z b z c z d z
torial
circuits 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1
0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1
Sequential y x x x x x x x x x x x x x x x x
circuits
x
1 1 x x 1 1 x x 1 1 x x 1 1 x x
FSMD
design
e f g
VHDL 1 0 0 1 1 0 0 0 0 0 1 1
0 0 0 1 1 1 0 1 1 1 0 1
y x x x x x x x x x x x x
x 1 0 x x 1 1 x x 1 1 x x
2/37
©
R.Lauwereins
Imec 2001
Digital
• Step 2: determine all prime implicants
design
w w w w
Combina- a z b z c z d z
torial
circuits 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1
0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1
Sequential y x x x x x x x x x x x x x x x x
circuits
x
1 1 x x 1 1 x x 1 1 x x 1 1 x x
FSMD
design
e f g
VHDL 1 0 0 1 1 0 0 0 0 0 1 1
0 0 0 1 1 1 0 1 1 1 0 1
x 1 0 x x 1 1 x x 1 1 x x
2/38
©
R.Lauwereins
Imec 2001
Digital
• Step 3: Determine all essential prime
design
implicants
Combina-
torial w w w w
circuits
a z b z c z d z
Sequential 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1
circuits
0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1
y x x x x x x x x x x x x x x x x
FSMD
x
design 1 1 x x 1 1 x x 1 1 x x 1 1 x x
Complete Complete Complete Complete
VHDL
coverage coverage coverage coverage
e f g
1 0 0 1 1 0 0 0 0 0 1 1
0 0 0 1 1 1 0 1 1 1 0 1
x 1 0 x x 1 1 x x 1 1 x x
Complete Complete Incomplete

2/39 coverage coverage coverage
©
R.Lauwereins
Imec 2001
Digital
• Step 4: Determine minimum coverage
design
Combina-
g Selection of the cube that realises
torial
0 0 1 1 the remaining minterm:
circuits
1 1 0 1 - Select all cubes that realise
Sequential x x x x the minterm and are already
circuits essential for another function;
1 1 x x
in this case, both are already
FSMD essential
design
- Select that cube that appears
VHDL
in the smallest number of
other functions to keep the
fan-out as low as possible
2/40
©
R.Lauwereins
Imec 2001
Digital
• Note down the standard form
design
Combina-
w y’w’
torial
circuits z
a z yw
1 0 1 1
x
Sequential
circuits
0 1 1 1
y x x x x
FSMD
x
design 1 1 x x
VHDL
a=y’w’+z+yw+x
2/41
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
w y’w’
torial
circuits z
b z yw
1 1 1 1
x
Sequential
circuits y’
1 0 1 0 z’w’
x x x x zw
FSMD
design 1 1 x x
VHDL
a=y’w’+z+yw+x
b=y’+z’w’+zw
2/42
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
w y’w’
torial
circuits z
c z yw
1 1 1 0
x
Sequential
circuits y’
1 1 1 1 z’w’
x x x x zw
FSMD
design 1 1 x x
z’
w
y
VHDL
a=y’w’+z+yw+x
b=y’+z’w’+zw
c=z’+w+y
2/43
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
w y’w’
torial
circuits z
d z yw
1 0 1 1
x
Sequential
circuits y’
0 1 0 1 z’w’
x x x x zw
FSMD
design 1 1 x x
z’
w
y
VHDL
y’z
yz’w
a=y’w’+z+yw+x zw’
b=y’+z’w’+zw
c=z’+w+y
d=y’w’+y’z+yz’w+zw’+x
2/44
©
R.Lauwereins
Imec 2001
Digital
design
Combina- y’w’
torial
circuits z
e yw
1 0 0 1
x
Sequential
circuits y’
0 0 0 1 z’w’
y x x x x zw
FSMD
design x 1 0 x x
z’
w
y
VHDL
y’z
yz’w
b=y’+z’w’+zw
c=z’+w+y
e=y’w’+zw’
2/45
©
R.Lauwereins
Imec 2001
Digital
design
Combina- y’w’
torial
circuits z
f yw
1 0 0 0
x
Sequential
circuits y’
1 1 0 1 z’w’
x x x x zw
FSMD
design 1 1 x x
z’
w
y
VHDL
y’z
yz’w
b=y’+z’w’+zw yz’
yw’
c=z’+w+y
e=y’w’+zw’
f=z’w’+yz’+yw’+x
2/46
©
R.Lauwereins
Imec 2001
Digital
design
Combina- y’w’
torial
circuits z
g yw
0 0 1 1
x
Sequential
circuits y’
1 1 0 1 z’w’
x x x x zw
FSMD
design 1 1 x x
z’
w
y
VHDL
y’z
yz’w
b=y’+z’w’+zw yz’
yw’
c=z’+w+y
e=y’w’+zw’
f=z’w’+yz’+yw’+x
2/47 g=y’z+yz’+yw’+x
©
R.Lauwereins
Imec 2001
Digital xyzw
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
a b c d e f g
2/48
©
R.Lauwereins
Imec 2001
Digital
• Cost when realising as (1-minterms):
design
 a: 4*1+8*(4+1)+1*(8+1)=53
Combina-  b: 4*1+8*(4+1)+1*(8+1)=53
torial
circuits  c: 4*1+9*(4+1)+1*(9+1)=59
 d: 4*1+7*(4+1)+1*(7+1)=47 329 (100%)
Sequential
circuits  e: 4*1+4*(4+1)+1*(4+1)=29
 f: 4*1+6*(4+1)+1*(6+1)=41
FSMD
design  g: 4*1+7*(4+1)+1*(7+1)=47
• Cost for minimal 2-layer-implementation
VHDL
 Invertors: 4*1=4
 AND-gates: 8*(2+1)+1*(3+1)=28
 OR-gates: 1*(2+1)+2*(3+1)+3*(4+1) 64 (19%)
+1*(5+1)=32
2/49
©
R.Lauwereins
Imec 2001
Digital
• Delay when realising as (1-minterms):
design
 Critical path=c (9-input OR)
Combina-  c: (1)+(.6+4*.4+1)+(.6+9*.4+1)=9.4 (100%)
torial
circuits • Delay for minimal 2-layer-implementation
 Critical path=d (3-input AND & 5-input OR)
Sequential
circuits  d: (1)+(.6+3*.4+1)+(.6+5*.4+1)=7.4 (79%)
FSMD
design
VHDL
2/50
©
R.Lauwereins
Imec 2001
Digital
design
 Karnaugh map
torial
 Quine-McCluskey
Sequential
FSMD
design
VHDL MUX, …)
2/51
©
R.Lauwereins
Imec 2001
Quine-McCluskey
Digital
• Method with Karnaugh map
design
 OK for human minimisation : visually oriented
Combina-  no guarantee for optimum solution
torial
circuits • Computer method
 Quine-McCluskey
Sequential
circuits  table oriented
 leads to optimum solution
FSMD
design  is the basis of all CAD circuit design tools
VHDL
 hardly doable by hand
2/52
©
R.Lauwereins
Imec 2001
Digital
design
Combina-  Gate arrays: NAND, NOR
torial
circuits  Custom library: AOI, OAI, …
 PLA
Sequential
circuits  FPGA
FSMD
design
VHDL MUX, …)
2/53
©
R.Lauwereins
Imec 2001
Digital
design
Combina-  Gate arrays: NAND, NOR
torial
 PLA
Sequential
circuits  FPGA
FSMD
design
VHDL MUX, …)
2/54
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Properties of the methodology followed:
design
 When minimizing 1-minterms: INV-AND-OR
Combina-  When minimizing 0-maxterms: INV-OR-AND
torial
circuits  Any function can be realized in two layers of
logic with this methodology
Sequential
circuits
 The fan-in of the gates can become arbitrary
large
FSMD
design
• Properties of gate arrays:
 They only contain m-input NAND or m-input
VHDL
NOR gates
• Technology mapping is:
 Translating a circuit consisting of INV-AND-OR
to one with only m-input NAND
 Dual: INV-OR-AND  m-input NOR
2/55
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Design flow:
design
Combina- Replace each n-input AND

torial
circuits
Decomposition (OR) by a few m-input
ANDs (ORs), with m<n
Sequential
circuits
Replace each AND and OR
FSMD Conversion by NAND or NOR
design
VHDL
Optimisation Eliminate double inversions
Try to make all input-output

Retiming
delays equal
2/56
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
• Conversion rules (based on the laws of De
Digital
design Morgan):
Combina-
torial
circuits
= (xy)’ = (x’ + y’)

Sequential
circuits
FSMD
design = (x+y)’ = (x’y’)
VHDL
• Optimisation rule:
= (x’)’ = x
2/57
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Conversion rules in practice:
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
The realisation with only NAND or only NOR is faster:

we save an invertor per gate!
2/58
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Realisation of an invertor:
design
Combina-
torial
circuits
Sequential
circuits
=
FSMD
design
VHDL
2/59
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Decomposition:
design
Combina-
torial
circuits
=
Sequential
circuits
FSMD
design
VHDL
2/60
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Retiming (delay optimisation): try to make
design
the delay from each input to the output
Combina- equal
torial
circuits • Example:
Sequential AND-OR implementation obtained from Karnaugh
circuits
minimisation
FSMD
design
VHDL
2/61
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Example (first possible decomposition in
design
3-input NAND):
Combina-
torial
circuits
Sequential
circuits
=
FSMD
design
VHDL
Delay = (.6+3x.4)+(1)+(.6+3x.4)+
(.6+3x.4)+(1)+(.6+3x.4)
= 9.2
2/62
Technology Mapping:
©
R.Lauwereins
Imec 2001
Gate Arrays
Digital
• Example (second possible decomposition
design
in 3-input NAND):
Combina-
torial
circuits
Sequential
circuits
=
FSMD
design
VHDL
Delay = (.6+3x.4)+(1)+(.6+3x.4)+
(.6+3x.4)
= 6.4 (70%)
2/63
©
R.Lauwereins
Imec 2001
Digital
design
torial
circuits  Custom library: AOI, OAI, …
 PLA
Sequential
circuits  FPGA
FSMD
design
VHDL MUX, …)
2/64
Technology Mapping:
©
R.Lauwereins
Imec 2001
Custom Library
Digital
• ASICs have AOI en OAI: small and fast!
design
• For small functions (not in course book):
Combina- Realise the inverse function with AND-OR
torial
circuits or OR-AND
Sequential
• Example: realise again following function:
circuits
F=(6,7,10,11,14,15,21,23,25,27,29,31)
FSMD
design  Realisation as sum of 1-minterms: cost = 90;
delay = 11
VHDL
 Minimal realisation as OR-AND: cost = 14
(16%); delay = 6.2 (56%)
2/65
Technology Mapping:
©
R.Lauwereins
Imec 2001
Custom Library
Digital • F=(6,7,10,11,14,15,21,23,25,27,29,31) 
design
F’= (0,1,2,3,4,5,8,9,12,13,16,17,18,19,20,
Combina-
torial 22,24,26,28,30)
circuits v
z z
Sequential
circuits F’ y v
w
x
y
FSMD 1 1 1 1 1 1 1 1 z
design
1 1 0 0 1 0 0 1
VHDL
x
1 1 0 0 1 0 0 1
w
1 1 0 0 1 0 0 1
F
F’
Cost=(5*1)+6=11 (12%)
Delay=1+(.6+6*.4)=4 (36%) F
2/66
Technology Mapping:
©
R.Lauwereins
Imec 2001
Custom Library
Digital
• For large functions:
design
Combina- Realise as AND-OR or OR-AND

torial
circuits
Sequential
circuits Transform to NAND or NOR
FSMD
design
Determine critical path
VHDL
Replace repeatedly 2 layers of

gates on critical path by AOI/OAI
Replace repeatedly 2 layers of

gates off critical path by AOI/OAI
2/67
Technology Mapping:
©
R.Lauwereins
Imec 2001
Custom Library
Digital
• F=w’z’+z(w+y)
design
Replace 2 gates on critical path by OAI AOI

Combina- Analyze
Realise with
Transform
Determine
Replace the
2 gates
to
the
other
AND
NAND
critical
onand
path
critical
andOR
path
NOR path by AOI
torial (2e possibility)
circuits
Sequential
circuits
FSMD y
design
w
F
VHDL
Cost=11
Cost=10
Cost=9
Cost=14
Cost=?
(64%)
(79%)
(71%)
Delay=3.8
Delay=?
Delay=5.2
Delay=5.6 (53%)
Delay=7.2
(72%)
(78%)
2/68
©
R.Lauwereins
Imec 2001
Digital
design
torial
 PLA
Sequential
circuits  FPGA
FSMD
design
VHDL MUX, …)
2/69
Technology Mapping:
©
R.Lauwereins
Imec 2001
PLA
Digital
• PLA is an AND-plane with large fan-in
design
followed by an OR-plane with large fan-in
Combina- • Technology mapping: realisation as AND-
torial
circuits OR, without the necessity for
Sequential
decomposition
circuits
FSMD
design
VHDL
2/70
©
R.Lauwereins
Imec 2001
Digital
design
torial
 PLA
Sequential
circuits  FPGA
FSMD
design
VHDL MUX, …)
2/71
Technology Mapping:
©
R.Lauwereins
Imec 2001
FPGA
• CLB is 2 functions of 4 variables or 1
Digital
design function of 5 variables
Combina-
• Technology mapping is similar as for
torial
circuits
custom design but i.o. AOI/OAI we search
for sub-circuits of 4 or 5 variables, first on
Sequential the critical path, next on the other paths
circuits
• For FPGAs technology mapping is done by
FSMD
design
automatic tools (see next slide); when
prototype: no hand optimalisation, when
VHDL final product: hand optimalisation
beneficial. Also for ASICs automatic tools
exist, hand optimalisation is beneficial
• BCD7-segment: create 7 truth tables
i.f.o. 4 variables: the rest is done by the
tools
2/72
Technology mapping:
©
R.Lauwereins
Imec 2001
FPGA
Digital
design
Combina-
torial
circuits
Sequential
circuits
FSMD
design
VHDL
Technology
mapping
2/73
©
R.Lauwereins
Imec 2001
Digital
design
Combina-
torial
 Correct timing behavior
circuits
Sequential MUX, …)
circuits
FSMD
design
VHDL
2/74
Correct timing behavior:
©
R.Lauwereins
Imec 2001
Hazard-free design
z
y
Digital
design x a
1 y’ F
Combina-
y
torial x 1 1 1
circuits z b
Sequential 0 1 2 3 4 5 6
circuits
FSMD x
design
y
VHDL
z
y’
F
2/75 Static 1-hazard
©
R.Lauwereins
Imec 2001
Hazard-free design
Digital • The hazard condition causes an unwanted
design
glitch!
Combina-
torial • Static 1-hazard: the output had to stay 1
circuits
but became briefly 0

Sequential
circuits
• Cause: different delay in two paths
FSMD
design
• Solution: see next slide
VHDL
2/76
©
R.Lauwereins
Imec 2001
Hazard-free design
z
y x a
Digital
design
y’ F
y
1 b
Combina- z
torial x 1 1 1 c
circuits
Sequential 0 1 2 3 4 5 6
circuits
x
FSMD
design
y
VHDL z
y’
2/77 F
©
R.Lauwereins
Imec 2001
Hazard-free design
Digital • Dynamic hazard: the output had to switch
design
(eg. from 1 to 0) but switched several
Combina-
torial times (bvb. 1  0  1  0)
circuits
• Cause: different delay in multiple paths
Sequential
circuits
• Example: see next slide
FSMD
design
VHDL
2/78
©
R.Lauwereins
Imec 2001
Hazard-free design
Digital
design
x’ x’’
a
F
Combina-
x
torial
circuits
Sequential
circuits 0 1 2 3 4 5 6 7 8 9
FSMD x
design
x’
VHDL
x’’
Statically equivalent to:
x F
2/79
©
R.Lauwereins
Imec 2001
Hazard-free design
Digital • Hazards are hard to detect by hand:
design
importance of simulation
Combina-
torial • The danger for hazards increases when
circuits
rise times and fall times are not equal

Sequential
circuits
• Are hazards a problem?
FSMD  For synchronous circuits, they are not
design
 Unless they control the clock of a memory
VHDL element
 For asynchronous circuits, they always are a
problem
 This is why asynchronous design is heavily
demotivated for FPGAs (the delay of the
different paths is only known after APR-
Automatic Placement and Routing)
2/80
©
R.Lauwereins
Imec 2001 Design of Combinatorial Circuits
Digital
design
Combina-
torial
• Basic RTL building blocks
circuits
 Ripple-carry adders
Sequential  Carry-look-ahead adders
circuits
 Adder/subtractors
FSMD  Multipliers
design
 Logic units
VHDL  Arithmetic-logic units
 Decoders
 Selectors
 Buses
 Priority encoders
 Magnitude comparators
 Shifters and rotators
2/81
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
 Ripple-carry adders
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
2/82
©
R.Lauwereins
Imec 2001
Ripple-carry adders
Digital
• Half adder
design
ci+1 yi si yi
xi yi ci+1 si
Combina-
torial 0 0 0 0
0 0 0 1
circuits 0 1 0 1
1 0 0 1 xi 0 1 xi 1 0
Sequential
circuits 1 1 1 0
FSMD
design xi yi
xi yi
VHDL
ci+1
HA
ci+1 si
1 CLB
si
2/83
©
R.Lauwereins
Imec 2001
Ripple-carry adders
Digital
• Full adder
design
xi yi ci ci+1 si yi yi
Combina- 0 0 0 0 0 ci+1 xi si xi
torial
0 0 1 0 1
circuits
0 1 0 0 1 1 1 1
Sequential 0 1 1 1 0 ci 1 1 1 ci 1 1
circuits
1 0 0 0 1
1 0 1 1 0
FSMD
design 1 1 0 1 0 xi
1 1 1 1 1
yi
VHDL ci
1 CLB
ci+1 si
2/84
Ripple-carry adders
• Full adder: alternative implementation
xi yi ci ci+1 si yi yi
0 0 0 0 0 xi xi
ci+1 si
0 0 1 0 1
0 1 0 0 1 1 1 1
0 1 1 1 0 ci 1 1 1 ci 1 1
1 0 0 0 1
1 0 1 1 0 xi
yi
1 1 0 1 0 ci
1 1 1 1 1
1 gate less, larger delay
from xi&yi to ci+1, same delay
from ci to ci+1
xi yi
ci+1 ci
FA si
2/85 si ci+1
©
R.Lauwereins
Imec 2001
Ripple-carry adders
Digital
• 4-bit ripple-carry adder
design
Combina-
torial x3 y3 x2 y2 x1 y1 x0 y0
circuits
Sequential c4 c3 c2 c1 c0=0
circuits FA FA FA FA
FSMD
design
s3 s2 s1 s0
VHDL
Critical path: x0 or y0 to c4: 1 XOR + 4 AND + 4 OR
In principal 1 CLB per bit

Because of special circuitry (dedicated carry chain):
1 CLB per 2 bits
2/86
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
Sequential  Carry-look-ahead adders
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
2/87
©
R.Lauwereins
Imec 2001
Carry-look-ahead adders
Digital
• Ripple-carry adder is slow because the
design
critical path x0 to cn+1 is long
Combina- • Speed-up is possible by computing for
torial
circuits
example c4 directly (in principle in 2
Sequential layers of logic) from c0, x0…x3 en y0…y3.
circuits
Hence the name Carry-look-ahead
FSMD
design
• How is this done? See exercises and
course book
VHDL xi…i+3 yi…i+3
ci+4 4-bit CLA ci
si…i+3
2/88
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
 Adder/subtractors
design
 Logic units
 Decoders
 Selectors
 Buses
2/89
©
R.Lauwereins
Imec 2001
Adder-subtractors
X Y
Digital S Function Note
design
0 X+Y Addition Cout Adder/ S
Combina- 1 X-Y=X+Y*=X+Y’+1 Subtraction subtractor
torial
circuits
F
Sequential x3 y3 x2 y2 x1 y1 x0 y0
circuits
S
FSMD
design
VHDL
c4 c3 c2 c1 c0
FA FA FA FA
f3 f2 f1 f0
2/90 overflow Only for 2-complement!!!

©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
FSMD  Multipliers
design
 Logic units
 Decoders
 Selectors
 Buses
2/91
©
R.Lauwereins
Imec 2001
Multipliers
Digital
• A 1-bit by 1-bit multiplier:
design
C=B•A
Combina-
torial
b0 b0 a0 c0=a00.b00
circuits
0 0 0
a0
Sequential
0 1 0
circuits a0 b0 1 0 0
1 1 1
FSMD
design
A 1-bit by 1-bit multiplier is hence an AND gate

VHDL
a0 b0
c0
2/92
©
R.Lauwereins
Imec 2001
Multipliers
Digital
• A 2-bit by 2-bit multiplier:
design
C=B•A
Combina-
torial
circuits a0
b1 b0 b1 b0
Sequential
circuits a1 a0
a1 b0
a 0 b1 a0 b0 b1
FSMD
design
a1 b1 a 1 b0
VHDL
c3 c2 c1 c0
HA HA
c3 c2 c1 c0
Each of these
terms is a
1-bit by 1-bit
multiplier: AND
2/93
©
R.Lauwereins
Imec 2001
Multipliers
Digital
• A 4-bit by 3-bit multiplier: cost=O(n2)
design
a0 b0
b3 b2 b1
Combina-
torial
circuits a1 b0
b3 b2 b1
Sequential 0
circuits
FSMD
4-bit adder
design cout s3 s2 s1 s0
VHDL a2 b0
b3 b2 b1
4-bit adder
cout s3 s2 s1 s0
c6 c5 c4 c3 c2 c1 c0
2/94
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
2/95
©
R.Lauwereins
Imec 2001
Logic units
Digital
• Goal: implement a unit that can realise all
design
16 Boolean functions of 2 bits
Combina- • The unit has two inputs X and Y and 4
torial
circuits select bits S3S2S1S0 that select the
Sequential wanted function
circuits
• The coding of the select bits is identical
FSMD
design
to the function number in the table of
possible Boolean functions
VHDL
2/96
©
R.Lauwereins
Imec 2001
Logic units
Function value
Digital for x,y
design
1-minterms 00 01 10 11 Expression
Combina- - 0 0 0 0 F0=0
torial
circuits
m3 0 0 0 1 F1=xy
m2 0 0 1 0 F2=xy’
Sequential m2+m3 0 0 1 1 F3=x
circuits
m1 0 1 0 0 F4=x’y
m1+m3 0 1 0 1 F5=y
FSMD
design m1+m2 0 1 1 0 F6=xy’+x’y
m1+m2+m3 0 1 1 1 F7=x+y
VHDL
m0 1 0 0 0 F8=(x+y)’
m0+m3 1 0 0 1 F9=xy+x’y’
m0+m2 1 0 1 0 F10=y’
m0+m2+m3 1 0 1 1 F11=x+y’
m0+m1 1 1 0 0 F12=x’
m0+m1+m3 1 1 0 1 F13=x’+y
m0+m1+m2 1 1 1 0 F14=(xy)’
m0+m1+m2+m3 1 1 1 1 F15=1
2/97
©
R.Lauwereins
Imec 2001
Logic units
Digital
design
xi
Combina- yi
torial S0
circuits S1
S2 xi yi
Sequential S3
circuits
FSMD S0..3 LU
design
VHDL
fi
fi
2/98
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
VHDL  Arithmetic-logic units
 Decoders
 Selectors
 Buses
2/99
©
R.Lauwereins
Imec 2001
Arithmetic-logic units
Digital
• Goal: build a unit that realises 4
design
arithmetic operations (addition,
Combina- subtraction, increment and decrement)
torial
circuits and 4 logic operations (AND, OR, INV,
identity)
Sequential
circuits • Realisation principle: use an adder in
FSMD front of which we place a modifier circuit
design
(Arithmetic-Logic Extender)
VHDL • This principle has already been applied
for the 2-complement adder/subtractor:
this was an adder in front of which we
placed an exor circuit to allow for
subtraction
2/100
©
R.Lauwereins
Imec 2001
Digital
a4 b4 a 3 b3 a 2 b2 a 1 b1 a0 b0
design
Combina-
torial
circuits
S
Sequential
circuits
FSMD
design
VHDL FA FA FA FA FA
Cout
f4 f3 f2 f1 f0
S selects the function to be executed:

0=addition, 1=subtraction
2/101
©
R.Lauwereins
Imec 2001
Digital
a 4 b4 a3 b3 a2 b2 a1 b1 a0 b0
design
S01
Combina-
torial
circuits
M
Sequential
circuits
ALE ALE ALE ALE ALE

FSMD
design
X Y
VHDL FA FA FA FA FA
Cout
f4 f3 f2 f1 f0
M selects the type of operation: 0=logic, 1=arithmetic

S0 and S1 select the operation
2/102
©
R.Lauwereins
Imec 2001
Digital MMM SS111 S

S
S000 Function
Function
Function
Function F
FF XXX YY Y CCC0
000
design 000 00 0
00 Complement
Complement
Complement A’
A’
A’ A’A’ 000 000
Complement A’
000 00 1
11 AND
AND A
AAND
A AND
AND BB AAAND
ANDBB 00 00
Combina-
torial 000 11 00 Identity AA AA 00 00
circuits 000 11 11 OR A
A OR
OR BB AAOR
ORBB 00 00
111 00 00 Decrement
Decrement A-1
A-1 AA all
all11 00
Sequential
circuits 111 00 11 Add A+B
A+B AA BB 00
11 11 00 Subtract
Subtract A-B
A-B AA B’B’ 11
FSMD 1 1 1 Increment A+1 A all 0 1
design
VHDL
2/103
©
R.Lauwereins
Imec 2001
M S1 S0 Function F X Y C0
Digital 0 0 0 Complement A’ A’ 0 0
design
0 0 1 AND A AND B A AND B 0 0
Combina-
0 1 0 Identity A A 0 0
torial 0 1 1 OR A OR B A OR B 0 0
circuits
1 0 0 Decrement A-1 A all 1 0
1 0 1 Add A+B A B 0
Sequential
circuits 1 1 0 Subtract A-B A B’ 1
1 1 1 Increment A+1 A all 0 1
FSMD
design
VHDL
S0
c0 M S1
S1
M 1 1
c0
2/104
©
R.Lauwereins
Imec 2001
design
Combina-
circuits
1 0 1 Add A+B A B 0
Sequential
FSMD
design
a
M b
VHDL
S0 S0 S0
X S1 S1 S1
M
1
1 1
bi
1 1 1 1 1 1 1
ai
1 1 1 1 1 1
2/105 X
©
R.Lauwereins
Imec 2001
design
Combina-
circuits
1 0 1 Add A+B A B 0
Sequential
FSMD
design
a
M b
VHDL
S0 S0 S0
Y S1 S1 S1
M
1 1
1 1
bi
1 1
ai
1 1
Y
2/106
©
R.Lauwereins
Imec 2001
Digital
a 4 b4 a3 b3 a2 b2 a1 b1 a0 b0
design
S01
Combina-
torial
circuits
M
Sequential
circuits
ALE ALE ALE ALE ALE

FSMD
design
X Y
VHDL FA FA FA FA FA
Cout
f4 f3 f2 f1 f0
2/107
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
2/108
©
R.Lauwereins
Imec 2001
Decoders
Digital E A1 A0 C3 C2 C1 C0
design
0 0 0 0 0 0 0 E
0 0 1 0 0 0 0 A1
Combina-
torial 0 1 0 0 0 0 0 A0
circuits
0 1 1 0 0 0 0
1 0 0 0 0 0 1
Sequential
circuits 1 0 1 0 0 1 0
1 1 0 0 1 0 0
FSMD
1 1 1 1 0 0 0 C3 C2 C1 C0
design
VHDL
A1..0
E
Decoder
C3..0 2 CLB
2/109
©
R.Lauwereins
Imec 2001
Decoders
Digital A3..2
design
Combina- E
torial Decoder
circuits
Sequential
circuits
FSMD
design A1..0 A1..0 A1..0 A1..0
VHDL
E E E E
Decoder Decoder Decoder Decoder
C15..12 C11..8 C7..4 C3..0
2/110
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
2/111
©
R.Lauwereins
Imec 2001
Selectors
D3 D2 D1 D0
Digital S1 S0 Y
design
S1
0 0 D0
S0
0 1 D1
Combina-
torial 1 0 D2
circuits
1 1 D3
Sequential
circuits
FSMD
design Y
VHDL
D3..0
In principle:
2-to-1 MUX is 1/2 CLB
S1..0 4-to-1
Due to special provisions:
MUX
4-to-1 MUX is 1 CLB
Y
2/112
©
R.Lauwereins
Imec 2001
Selectors
D3 D2 D1 D0
Digital S1 S0 Y
design
S1
Decoder
0 0 D0
0 1 D1
Combina- S0
torial 1 0 D2
circuits
1 1 D3
Sequential
circuits
FSMD
design
Y
VHDL
Alternative implementation
2/113
©
R.Lauwereins
Imec 2001
Selectors
Digital
design
D15..12 D11..8 D7..4 D3..0
Combina-
torial
circuits S1..0 S1..0 S1..0 S1..0
4-to-1 4-to-1 4-to-1 4-to-1
Sequential
circuits selector selector selector selector
FSMD
design
VHDL
S3..2
4-to-1
selector
Y
2/114
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
2/115
©
R.Lauwereins
Imec 2001
Buses
Digital
• Problem with high fan-in MUX:
design
 fan-in OR gate too big
Combina-  all inputs have to be routed to 1 central
torial
circuits
location: substantial routing delay and difficult
routing
Sequential
circuits
• Solution: bus with tristate drivers
FSMD
design D3 D2 D1 D0 S1 S0
VHDL E Y
Decoder
0 Z
1 D
2/116 Y
©
R.Lauwereins
Imec 2001
Buses
Digital
• In an FPGA (lab session) a limited number
design
of tristate buffers is foreseen, connected
Combina- to horizontal long lines. It is possible to
torial
circuits indicate for a certain signal that we
prefer to map it to a long line.
Sequential
circuits • Note that a Boolean signal already can
FSMD have 4 different values:
design
 0: the logical signal “0”
VHDL  1: the logical signal “1”
 x: don’t care
 Z: high-impedant
• Simulations will allow to visualize each of
the 4 different values
2/117
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
 Priority encoders
2/118
©
R.Lauwereins
Imec 2001
Priority encoders
D0
D3 D2 D1 D0 A1 A0 Any Any D1
Digital
design 0 0 0 0 0 0 0 0
0 0 0 1 0 0 1
Combina-
0 0 1 0 0 1 1 D2
torial
circuits 0 0 1 1 0 1 1 D3
0 1 0 0 1 0 1
Sequential
0 1 0 1 1 0 1 D0
circuits
A1 D1
0 1 1 0 1 0 1
FSMD 0 1 1 1 1 0 1 0 0 0 0
design
1 0 0 0 1 1 1
1 0 0 1 1 1 1 D2
VHDL
1 0 1 0 1 1 1 D3
1 0 1 1 1 1 1
1 1 0 0 1 1 1 D0
A0 D1
1 1 0 1 1 1 1
1 1 1 0 1 1 1 1 1
1 1 1 1 1 1 1
D2
1 1 1 1
D3
2/119 1 1 1 1
©
R.Lauwereins
Imec 2001
Priority encoders
D0
Any D1
Digital
design D3
0
D0
Combina- D2
torial
circuits D3
Sequential D0
circuits
A1 D1
FSMD
design
0 0 0 0
Any A1 A0 D2
VHDL
D3
D3..0 D0
A0 D1
Any Priority
1 1/2 CLB 1 1
encoder
D2
1 1 1 1
A1..0 D3
2/120 1 1 1 1
©
R.Lauwereins
Imec 2001
Priority encoders
Digital
design D15..12 D11..8 D7..4 D3..0
Combina-
torial Priority Priority Priority Priority
circuits
encoder encoder encoder encoder
Sequential
circuits
FSMD
design
VHDL
Any Priority 4-to-1 4-to-1

encoder MUX MUX
A3..2 A1 A0
2/121
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
 Magnitude comparators
2/122
©
R.Lauwereins
Imec 2001
Magnitude comparators
y0
Digital x1 y11 x00 y00
y G (X>Y)
G (X>Y) LL (X<Y)
(X<Y) G x0
design
0 0 0 0
0 0
0 00
Combina- 0 0 0 1
1 0
0 11 1
torial 0 0 1 0
0 1
1 00
circuits y1
0 0 1 1
1 0
0 00 1
x1
Sequential 0 1 0 0
0 0
0 11 1 1 1 1
circuits 0 1 0 1 0 11
1 0
0 1 1 0
0 0
0 11
FSMD
design 0 1 1 1
1 0
0 11 y0
1 0 0 0
0 1
1 00 L x0
VHDL 1 0 0 1
1 1
1 00
1
1
1 0
0 1
1 0
0 1
1 00
1 1 1 1
1
1 0
0 1
1 1
1 1
1 00 y1
1
1
1 1
1 0
0 0
0 0
0 00 x1
1
1 1
1 0
0 1
1 0
0 11
1
1 1
1 1
1 0
0 1
1 00
1
1 1
1 1
1 1
1 0
0 00
2/123
©
R.Lauwereins
Imec 2001
y0
Digital
design G x0
x1
Combina- x0 1
torial y1
circuits y0 y1
1
x1
Sequential 1 1 1 1
circuits
FSMD
design
y0
L x0
VHDL
1
G L 1 1 1 1
y1
Xi Yi 1
x1
Gi+1 Gi
Comp
Li+1 Li 1 CLB
2/124
©
R.Lauwereins
Imec 2001
Digital x7 y 7 x6 y 6 x5 y 5 x4 y 4 x3 y 3 x2 y 2 x1 y 1 x0 y 0
design
Combina-
G
torial Comp Comp Comp Comp Comp Comp Comp
circuits L
Sequential
circuits
x7 y 7 x6 y 6 x5 y 5 x4 y 4 x3 y 3 x2 y 2 x1 y 1 x0 y 0
FSMD
design
Comp Comp Comp Comp
VHDL
Comp Comp
Comp
G L
2/125
©
R.Lauwereins
Imec 2001
Digital
• Simpler circuits are used for comparison
design
with constants!!
Combina- X X
torial x7 x6
circuits
X is
Sequential
circuits 8 bits
y
FSMD
design
y=1 when X>=64
VHDL
y y x7 x6
y=1 when X=0 y=1 when X=255
x0
y
y y=1 when X<192
y=1 when X is even

2/126
©
R.Lauwereins
Digital
design
Combina-
torial
circuits
circuits
design
 Logic units
 Decoders
 Selectors
 Buses
 Shifters and rotators
2/127
©
R.Lauwereins
Imec 2001
Shifters and rotators
• Shifter:
Digital  An input word is shifted m positions to the left
design
or to the right
Combina-  m bits disappear at one side
torial
circuits  m bits are created at the other side
 For an arithmetic shift (word = 2-complement)
Sequential
circuits
For a left shift m zeros are shifted in
FSMD from the right
design
For a right shift m times the MSB is
VHDL shifted in from the left (for 2-
complement)
 For a logic shift
It is possible to indicate which value
is shifted in
 m bit left shift is multiplication with 2m
2/128
 m bit right shift is division by 2m
©
R.Lauwereins
Imec 2001
• Rotator:
Digital
design  An input word is shifted m positions to the left
or to the right
Combina-
torial  The bits that drop-off at one side, are shifted
circuits back in at the other side
Sequential
circuits
FSMD
design
VHDL
2/129
©
R.Lauwereins
Imec 2001
S2: 0=no shift,1=shift S1: 0=left,1=right S0: 0=shift,1=rotate
Digital
design d0
d1
Combina-
d2
torial d3
circuits S2
S1
Sequential S0
circuits L-in
R-in
FSMD
design
M M
VHDL
4-to-1 4-to-1 4-to-1 4-to-1

MUX MUX MUX MUX
y3 y2 y1 y0
2/130
©
R.Lauwereins
Imec 2001
Digital
design
8-bit barrel left rotator
Combina-
torial
circuits
Sequential
circuits
S0 M M M M M M M M
FSMD
design
VHDL
S1 M M M M M M M M
S2 M M M M M M M M
2/131

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Delay = (gate-delay)critical path = 1 +

0 x’y’z’ x’y’z x’yz x’yz’ x’z (y does not matter)

xz’ (y does not matter)

Cost = 3*(1) + {1*(2+1)+2*(3+1)}

Differs from course book

FSMD Determine all prime implicants

Determine all essential

Search for minimal coverage

Combina- wxyz wxyz

Cost=4*1+2*(3+1)+2*(2+1) Cost =4*1+1*(3+1)+2*(2+1)

Is already the minimum coverage

Cost=1+(4*(3+1))+(1*(4+1))=22 (76% cheaper)

Is already the minimum coverage

Cost=(1*1)+(3*(2+1))+(1*(3+1))=14 (84% cheaper)

Realisation Cost Rel. cost Delay Rel. delay

VHDL We’ll see that, depending on the technology mapping,

Complete Complete Incomplete

Combina- Replace each n-input AND

Optimisation Eliminate double inversions

Try to make all input-output

= (xy)’ = (x’ + y’)

The realisation with only NAND or only NOR is faster:

Combina- Realise as AND-OR or OR-AND

Replace repeatedly 2 layers of

Replace repeatedly 2 layers of

Replace 2 gates on critical path by OAI AOI

but became briefly 0

Statically equivalent to:

rise times and fall times are not equal

Critical path: x0 or y0 to c4: 1 XOR + 4 AND + 4 OR

In principal 1 CLB per bit

ci+4 4-bit CLA ci

2/90 overflow Only for 2-complement!!!

A 1-bit by 1-bit multiplier is hence an AND gate

S selects the function to be executed:

ALE ALE ALE ALE ALE

M selects the type of operation: 0=logic, 1=arithmetic

Digital MMM SS111 S

ALE ALE ALE ALE ALE

C15..12 C11..8 C7..4 C3..0

Any Priority 4-to-1 4-to-1

y=1 when X=0 y=1 when X=255

y y=1 when X<192

y=1 when X is even

4-to-1 4-to-1 4-to-1 4-to-1

You might also like

Cost = 3(1) + {1(2+1)+2*(3+1)}

Cost=41+2(3+1)+2(2+1) Cost =41+1(3+1)+2(2+1)

Cost=1+(4(3+1))+(1(4+1))=22 (76% cheaper)

Cost=(11)+(3(2+1))+(1*(3+1))=14 (84% cheaper)