BITS Pilani

Pilani Campus

DIGITAL systems (Combinational circuit)

RKTiwary
Mano
Chapter 4:

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BCD Adder
+ x3 x2 x1 x0
4-bits plus 4-bits
Operands and Result: 0 to 9 + y3 y2 y1 y0
────────
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
Cy S3 S2 S1 S0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0

0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0

1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0

9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Wrong BCD Value

0001 1000

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BCD Adder

X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16 
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17 
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18 
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19 
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20 
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21 
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22 
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23 
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24 

+6

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BCD Adder
Correct Binary Adder’s Output (+6)
▪ If the result is between ‘A’ and ‘F’
▪ If Cy = 1

S3 S2 S1 S0 Err
S1
0 0 0 0 0

1 0 0 0 0 S2
1 0 0 1 0 1 1 1 1
S3 1 1
1 0 1 0 1
S0
1 0 1 1 1
1 1 0 0 1
Err = S3 S2 + S3 S1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1 Err = C + S3 S2 + S3 S1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BCD Adder
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

0 0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Cy S3 S2 S1 S0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Binary Subtractor

Use 2’s complement with binary adder

▪ x – y = x + (-y) = x + y’ + 1

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Binary Adder/Subtractor

M: Control Signal (Mode)

▪ M=0  F = x + y
▪ M=1  F = x – y
x3 x2 x1 x0 y3 y2 y1 y0 M

A3 A2 A1 A0 B 3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F 2 F 1 F 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

2 Bit Binary Multiplier

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Multiplicand 4 bit Multiplier 3 Bit

A bit of the multiplier is ANDed with

each bit of the multiplicand in as
many levels as there are bits in the
multiplier.
The binary output in each level of
AND gates is added with the partial
product of the previous level to form a
new partial product.
The last level produces the product.
For J multiplier bits and K
multiplicand bits,
We need J X K AND gates and
(J – 1) K -bit adders to produce a
product of (J + K) bits.
If there are more bits then instead of
HA , FA is used

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 MAGNITUDE COMPARATOR

 𝐴 = 𝐴3 𝐴2 𝐴 1 𝐴 0 ; 𝐵 = 𝐵3 𝐵 2 𝐵1 𝐵0

 Three outputs

)=

  A

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

A3 ‘ B 3
A3B3 +A3’B3’
A3B3’

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956