Microprocessor Systems and Interfacing (Eee342) : Dr. Omer Chughtai Assistant Professor, CUI, Wah Campus Email

MICROPROCESSOR SYSTEMS AND
INTERFACING (EEE342)
Dr. Omer Chughtai
Assistant Professor, CUI, Wah Campus

Email: omer.chughtai@outlook.com
ADDRESSING MODES
8086 Microprocessor
Addressing Modes
Every instruction of a program has to operate on a data.

The different ways in which a source operand is denoted
in an instruction are known as addressing modes.
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports
11. Relative Addressing Group IV : Relative Addressing mode
12. Implied Addressing Group V : Implied Addressing mode

3
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data
1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL
7. Based Index Addressing (CL)  (DH)
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
4
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
Example:
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
7. Based Index Addressing (DL)  08H

MOV AX, 0A9FH
10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
(AX)  0A9FH
5
8086 Microprocessor
Addressing Modes : Memory Access
20 Address lines  8086 can address up to

220 = 1M bytes of memory
However, the largest register is only 16 bits
Physical Address will have to be calculated

Physical Address : Actual address of a byte in
memory. i.e. the value which goes out onto the
address bus.
Memory Address represented in the form –

Seg : Offset (Eg - 89AB:F012)
Each time the processor wants to access

memory, it takes the contents of a segment
register, shifts it one hexadecimal place to the
16 bytes of
left (same as multiplying by 1610), then add the contiguous memory
required offset to form the 20- bit address
89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
7
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
2. Immediate Addressing
Here, the effective address of the memory
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]

The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents of
11. Relative Addressing the memory location into BX register.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
9
1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.
3. Direct Addressing Registers used to hold EA are any of the following

registers:
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
address calculation.
Example:
Note : Register/ memory
8. String Addressing enclosed in brackets refer
MOV CX, [BX]
to content of register/
9. Direct I/O port Addressing memory
Operations:
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA +1)
10
1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.
5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is
used.
Example:
MOV AX, [BX + 08H]
Operations:
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA
(AX)  (MA) or,
(AL)  (MA) 11
(AH)  (MA + 1)
1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.
5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.

Example:
MOV CX, [SI + 0A2H]
Operations:
FFA2H  A2H (Sign extended)
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA + 1)
12
1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
Example:
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
000AH  0AH (Sign extended)
8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA
10. Indirect I/O port Addressing (DX)  (MA) or,
(DL)  (MA)
12. Implied Addressing (DH)  (MA + 1)
13
1. Register Addressing Employed in string operations to operate on string

data.
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored
in DI register.
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES

Example: MOVS BYTE
Operations:
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA
11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
Note : Effective address of (MAE)  (MA)

the Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI)
14+ 1
8086 Microprocessor Group III : Addressing
Addressing Modes modes for I/O ports
1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.
4. Register Indirect Addressing Example: IN AL, [09H]
5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
7. Based Index Addressing Content of port with address 09H is

moved to AL register
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)
Content of AX is moved to port

whose address is specified by DX
register. 15
8086 Microprocessor Group IV : Relative
Addressing Modes Addressing mode
3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
Operations:
8. String Addressing 000AH  0AH (sign extend)
9. Direct I/O port Addressing If ZF = 1, then
10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps to
new address calculated above.
If ZF = 0, then next instruction of the

program is executed.
16
8086 Microprocessor Group IV : Implied
Addressing Modes Addressing mode
5. Based Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
operated by the instruction.
Example: CLC
This clears the carry flag to zero.
17
INSTRUCTION SET
8086 Microprocessor
Instruction Set
8086 supports 6 types of instructions.
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Process Control Instructions
6. Control Transfer Instructions
19
8086 Microprocessor
Instruction Set
Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.
Generally involve two operands: Source operand and

Destination operand of the same size.
Source: Register or a memory location or an immediate data

Destination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.
20
8086 Microprocessor
Instruction Set
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)
MOV reg/ mem, data
MOV reg, data (reg)  data

MOV mem, data (mem)  data
XCHG reg2/ mem, reg1
XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)
21
8086 Microprocessor
Instruction Set
PUSH reg16/ mem
PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)
PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)
POP reg16/ mem
POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2
POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2 22
8086 Microprocessor
Instruction Set
IN A, [DX] OUT [DX], A
IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)
IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)
IN A, addr8 OUT addr8, A
IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)
IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)
23
8086 Microprocessor
Instruction Set
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)
ADD reg/mem, data
ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data
ADD A, data
ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16
24
8086 Microprocessor
Instruction Set
ADC reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF
ADDC A, data
ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF
25
8086 Microprocessor
Instruction Set
SUB reg2/ mem, reg1/mem
SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)
SUB reg/mem, data
SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data
SUB A, data
SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16
26
8086 Microprocessor
Instruction Set
SBB reg2/ mem, reg1/mem
SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF
SBB reg/mem, data
SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF
SBB A, data
SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF
27
8086 Microprocessor
Instruction Set
INC reg/ mem
INC reg8 (reg8)  (reg8) + 1
INC reg16 (reg16)  (reg16) + 1
INC mem (mem)  (mem) + 1
DEC reg/ mem
DEC reg8 (reg8)  (reg8) - 1
DEC reg16 (reg16)  (reg16) - 1
DEC mem (mem)  (mem) - 1
28
8086 Microprocessor
Instruction Set
MUL reg/ mem
MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
IMUL reg/ mem
IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
29
8086 Microprocessor
Instruction Set
DIV reg/ mem
DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
30
8086 Microprocessor
Instruction Set
IDIV reg/ mem
IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
31
8086 Microprocessor
Instruction Set
CMP reg2/mem, reg1/ mem
CMP reg2, reg1 Modify flags  (reg2) – (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0
CMP reg2, mem Modify flags  (reg2) – (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0
CMP mem, reg1 Modify flags  (mem) – (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0
32
8086 Microprocessor
Instruction Set
CMP reg/mem, data
CMP reg, data Modify flags  (reg) – (data)
If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0
CMP mem, data Modify flags  (mem) – (mem)
If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0
33
8086 Microprocessor
Instruction Set
CMP A, data
CMP AL, data8 Modify flags  (AL) – data8
If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0
CMP AX, data16 Modify flags  (AX) – data16
If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0
34
8086 Microprocessor
Instruction Set
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
35
8086 Microprocessor
Instruction Set
36
8086 Microprocessor
Instruction Set
37
8086 Microprocessor
Instruction Set
38
8086 Microprocessor
Instruction Set
39
8086 Microprocessor
Instruction Set
40
8086 Microprocessor
Instruction Set
41
8086 Microprocessor
Instruction Set
42
8086 Microprocessor
Instruction Set
4. String Manipulation Instructions
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.
 REP instruction prefix : used to repeat execution of string instructions
 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.
 Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically

updated.
 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.
43
8086 Microprocessor
Instruction Set

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE While CX  0 and ZF = 1, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) – 1
ZF = 0)
REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of

string instruction and
(Repeat CMPS or SCAS until (CX)  (CX) - 1
ZF = 1)
44
8086 Microprocessor
Instruction Set

MOVS
MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) +

1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)

2 45
8086 Microprocessor
Instruction Set

Compare two string byte or string word
CMPS
CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation

1
For word operation

2 46
8086 Microprocessor
Instruction Set

Scan (compare) a string byte or word with accumulator
SCAS
SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
47
8086 Microprocessor
Instruction Set

Load string byte in to AL or string word in to AX
LODS
LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1
LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2
48
8086 Microprocessor
Instruction Set

Store byte from AL or word from AX in to string
STOS
STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2
49
8086 Microprocessor
Instruction Set
5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1
CLC Clear CF  0
CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0
STI Set interrupt enable flag IF  1
CLI Clear interrupt enable flag IF  0
NOP No operation
HLT Halt after interrupt is set
WAIT Wait for TEST pin active
ESC opcode mem/ reg Used to pass instruction to a coprocessor

which shares the address and data bus
with the 8086
LOCK Lock bus during next instruction 50

8086 Microprocessor
Instruction Set
Transfer the control to a specific destination or target instruction

Do not affect flags
 8086 Unconditional transfers
CALL reg/ mem/ disp16 Call subroutine
RET Return from subroutine
JMP reg/ mem/ disp8/ disp16 Unconditional jump
51
8086 Microprocessor
Instruction Set

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions
Checks flags
If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP
52
8086 Microprocessor
Instruction Set

 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions
Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0
JNE disp8 JNZ disp8 JNE disp8 JNZ disp8
Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal JBE disp8 JNA disp8
JLE disp8 JNG disp8 Jump if below or Jump if not above
Jump if less than Jump if not equal
or equal greater
53
8086 Microprocessor
Instruction Set
 8086 conditional branch instructions affecting individual flags
JC disp8 Jump if CF = 1
JNC disp8 Jump if CF = 0
JP disp8 Jump if PF = 1
JNP disp8 Jump if PF = 0
JO disp8 Jump if OF = 1
JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, Z = 1
JNZ disp8 Jump if result is not zero, i.e, Z = 1
54
Status Registers
Status Registers
Status Registers
Status Registers
Status Registers
Status Registers
Status Registers
Status Registers
Status Registers
Addition instructions
Instruction Operands Description

Addition
REG, memory
Algorithm:
memory, REG
operand1 = operand1 + operand2
ADD REG, REG
memory, immediate
Example:
REG, immediate
MOV AL, 5 ; AL = 5
ADD AL, -3 ; AL = 2
Add with Carry.
REG, memory Algorithm:

memory, REG operand1 = operand1 + operand2 + CF
ADC REG, REG
memory, immediate Example:
REG, immediate STC ; set CF = 1
MOV AL, 5 ; AL = 5
ADC AL, 1 ; AL = 7
Increment.
Algorithm:
operand = operand + 1
REG
INC
Memory
Example:
MOV AL, 4
INC AL ; AL = 5
; CF - unchanged!
Subtraction instructions

Subtract.
REG, memory memory, REG REG, Algorithm: operand1 = operand1 - operand2
SUB REG memory, immediate REG, Example:
immediate MOV AL, 5
SUB AL, 1 ; AL = 4
Subtract with Borrow.

REG, memory
Algorithm: operand1 = operand1 - operand2 – CF
memory, REG
Example:
SBB REG, REG
STC
memory, immediate
MOV AL, 5
REG, immediate
SBB AL, 3 ; AL = 5 - 3 - 1 = 1
Decrement.
Algorithm: operand = operand - 1
REG Example:
DEC
Memory MOV AL, 255 ; AL = 0FFh (255 or -1)
DEC AL ; AL = 0FEh (254 or -2)
; CF - unchanged!
Negate. Makes operand negative (two's complement).
Algorithm:
• Invert all bits of the operand
REG • Add 1 to inverted operand
NEG
Memory Example:
MOV AL, 5 ; AL = 05h
NEG AL ; AL = 0FBh (-5)
NEG AL ; AL = 05h (5)
Hardware Viewpoint
• CPU cannot distinguish signed from unsigned integers

– YOU, the programmer, give a meaning to binary numbers
• How the ADD instruction modifies OF and CF:
– CF = (carry out of the Most Significant Bit)
– OF = (carry out of the Most Significant Bit) XOR (carry into
the Most Significant Bit)
• Hardware does SUB by
– ADDing destination to the 2's complement of the source
operand
• How the SUB instruction modifies OF and CF:
– Negate (2's complement) the source and ADD it to
destination
– OF = (carry out of the MSB) XOR (carry into the MSB)
– CF = INVERT (carry out of the MSB)
Addition/subtraction examples
• Given the following initial state:

– AX = 1234h
– BL = ABh
– Memory location SUM = 00CDh
• Show the results of each step of the following instruction
sequence:
– ADD AX, [SUM] (AX) = (SUM) + (AX), 00CDh + 1234h = 1301h, (AX) = 1301h, (CF) = 0
– ADC BL, 05h (BL) = (BL) + 05h +(CF), ABh + 05h + 0 = B0h, (BL) = B0h, (CF) = 0
– NEG BL (BL) = –(BL), –B0h = –(1011 0000)2 = 0101 00002 = 50h
– SUB AX, 12h (AX) = (AX) – 0012h, 1301h – 0012h = 12EFh, (AX) = 12EFh, (CF) = 0
– INC WORD PTR [SUM] (SUM) = (SUM) + 1, 00CDh + 1 = 00CEh, (SUM) = 00CEh, (CF) = 0
ADD and SUB Examples
• For each of the following marked entries, show the values of the
destination operand and the six status flags:
• MOV AL,0FFh ; AL=-1

• ADD AL,1 ; AL=00h CF=1 OF=0 SF=0 ZF=1 AF=1
PF=1
• SUB AL,1 ; AL=FFh CF=1 OF=0 SF=1 ZF=0 AF=1
PF=1
• MOV AL,+127 ; AL=7Fh
• ADD AL,1 ; AL= -128 CF=0 OF=1 SF=1 ZF=0 AF=1
PF=0
• MOV AL,26h
• SUB AL,95h ; AL=91h CF=1 OF=1 SF=1 ZF=0 AF=0
PF=0
Multiplication/division
• Both signed and unsigned integer versions

• Register A is always one of the sources
• Destination always same; size-dependent
– Exception: signed multiplication does allow for slightly
different operation
• Easiest way to evaluate instructions: figure out
decimal values of operands, do operation in
decimal, then figure out binary/hex values of
results
MUL/IMUL

Unsigned multiply.
Algorithm: when operand is a byte:  AX =
AL * operand.
when operand is a word:  (DX AX) = AX *
REG
MUL operand.
Memory
Example:
MOV AL, 200; AL = 0C8h
MOV BL, 4
MUL BL ; AX = 0320h (800)
Signed multiply.
Algorithm: when operand is a byte:  AX = AL
* operand. when operand is a word:  (DX AX)
REG = AX * operand.
IMUL
Memory Example:
MOV AL, -2
MOV BL, -4
IMUL BL ; AX = 8
Byte: (AX) = (AL) * (S)
Word: (DX,AX) = (AX) * (S)
Double-word: (EDX,EAX) = (EAX) * (S)
Only CF, OF updated
If upper half of result = 0, CF & OF = 0
Otherwise, CF & OF = 1
MUL/IMUL
• When two bytes are multiplied −

– The multiplicand is in the AL register, and the multiplier is a byte in the memory or in
another register. The product is in AX. High-order 8 bits of the product is stored in AH
and the low-order 8 bits are stored in AL.
• When two one-word values are multiplied −

– The multiplicand should be in the AX register, and the multiplier is a word in memory
or another register. For example, for an instruction like MUL DX, you must store the
multiplier in DX and the multiplicand in AX.
• When two doubleword values are multiplied −

– When two doubleword values are multiplied, the multiplicand should be in EAX and the
multiplier is a doubleword value stored in memory or in another register. The product
generated is stored in the EDX:EAX registers, i.e., the high order 32 bits gets stored in
the EDX register and the low order 32-bits are stored in the EAX register.
Examples
• Given Consider that BH = FFh = (1111 1111)2

– EAX = 00000005h • As unsigned value, FFh = (255)10
– EBX = 0000FF02h • As signed value, FFh = (-1)10
• What are the results of the following instructions? (Assume all

instructions start with same values in registers above)
– MUL BL
AX = AL * BL = 05h * 02h = 5 * 2 = 10 10 = 000Ah
Unsigned multiplication
– MUL BH
AX = AL * BH = 05h * FFh = 5 * 255 = 1275 10 = 04FBh
Signed multiplication
– IMUL BH AX = AL * BH = 05h * FFh = 5 * -1 = -510 = FFFBh
DIV/IDIV

Unsigned divide.
Algorithm:
when operand is a byte:  AL = AX / operand,
AH = remainder (modulus)
REG when operand is a word:  AX = (DX AX) / operand
DIV
Memory DX = remainder (modulus)
Example:
MOV AX, 203 ; AX = 00CBh
MOV BL, 4
DIV BL ; AL = 50 (32h), AH = 3
Signed divide.
Algorithm:
when operand is a byte:  AL = AX / operand
AH = remainder (modulus)
REG when operand is a word:  AX = (DX AX) / operand
IDIV
Memory DX = remainder (modulus)
Example:
MOV AX, -203 ; AX = 0FF35h
MOV BL, 4
IDIV BL ; AL = -50 (0CEh), AH = -3 (0FDh)
Result split into quotient, remainder
Byte: (AL) = (AX) / (S), (AH) = (AX) % (S)
Word: (AX) = (DX,AX) / (S), (DX) = (DX,AX) % (S)
Dword: (EAX) = (EDX,EAX) / (S), (EDX) = (EDX,EAX) % (S)
Special “convert” instructions used to sign-extend value in register A before division
Flags undefined  Overflow causes exception
DIV/IDIV
• The division operation generates two elements - a quotient and a

remainder.
• When the divisor is 1 byte −
– The dividend is assumed to be in the AX register (16 bits). After division, the
quotient goes to the AL register and the remainder goes to the AH register.
• When the divisor is 1 word −
– The dividend is assumed to be 32 bits long and in the DX:AX registers. The high-
order 16 bits are in DX and the low-order 16 bits are in AX. After division, the
16-bit quotient goes to the AX register and the 16-bit remainder goes to the DX
register.
• When the divisor is doubleword −
Examples
• Given Consider that BH = FFh = (1111 1111)2

– EAX = 00000005h • As unsigned value, FFh = (255)10
– EBX = 0000FF02h • As signed value, FFh = (-1)10
• What are the results of the following instructions? (Assume all

instructions start with same values in registers above)
– DIV BL
AL = AX / BL = 0005h / 02h = 5 / 2 = 02h
AH = AX % BL = 0005h % 02h = 5 % 2 = 01h
– DIV BH Unsigned division
AL = AX / BH = 0005h / FFh = 5 / 255 = 00h
AH = AX % BH = 0005h / FFh = 5 % 255 = 05h
– IDIV BH Signed division
AL = AX / BH = 0005h / FFh = 5 / -1 = -5 = FBh
AH = AX % BH = 0005h % FFh = 5 % -1 = 00h

Microprocessor Systems and Interfacing (Eee342) : Dr. Omer Chughtai Assistant Professor, CUI, Wah Campus Email

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Microprocessor Systems and Interfacing (Eee342) : Dr. Omer Chughtai Assistant Professor, CUI, Wah Campus Email

Uploaded by

Copyright:

Available Formats

MICROPROCESSOR SYSTEMS AND

Dr. Omer Chughtai

Assistant Professor, CUI, Wah Campus

Every instruction of a program has to operate on a data.

4. Register Indirect Addressing

9. Direct I/O port Addressing

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

1. Register Addressing The instruction will specify the name of the

7. Based Index Addressing (CL)  (DH)

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

7. Based Index Addressing (DL)  08H

9. Direct I/O port Addressing

20 Address lines  8086 can address up to

However, the largest register is only 16 bits

Physical Address will have to be calculated

Memory Address represented in the form –

Each time the processor wants to access

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

5. Based Addressing The effective address is just a 16-bit number

1. Register Addressing In Register indirect addressing, name of the

3. Direct Addressing Registers used to hold EA are any of the following

1. Register Addressing In Based Addressing, BX or BP is used to hold the

5. Based Addressing When BX holds the base value of EA, 20-bit

(AX)  (MA) or,

1. Register Addressing SI or DI register is used to hold an index value for

5. Based Addressing In case of 8-bit displacement, it is sign extended

7. Based Index Addressing

(CX)  (MA) or,

1. Register Addressing In Based Index Addressing, the effective address

8. String Addressing EA = (BX) + (SI) + 000AH

1. Register Addressing Employed in string operations to operate on string

7. Based Index Addressing

11. Relative Addressing Calculation of destination memory location:

Note : Effective address of (MAE)  (MA)

1. Register Addressing These addressing modes are used to access data

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

7. Based Index Addressing Content of port with address 09H is

Content of AX is moved to port

3. Direct Addressing In this addressing mode, the effective address of

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

If ZF = 0, then next instruction of the

4. Register Indirect Addressing

11. Relative Addressing

12. Implied Addressing

8086 supports 6 types of instructions.

1. Data Transfer Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

Generally involve two operands: Source operand and

Source: Register or a memory location or an immediate data

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory