RISC machines

• reduced instruction set computer

vs. CISC -- complex ... (680x0, IBM 360,...)

• CISC technology has evolved highly complex

instruction sets, to bridge "semantic gap"
between hardware and software

- simplify compilers

- alleviate software crisis

- improve architecture quality

• But has CISC design gone "over the top"?

• if one looks at the software being executed,

it is typically simple and unsophisticated, and
do not exploit the sophisticated features of
CISC instruction sets

B. Ross COSC 3p92 1

 Software studies (statistical analysis)

Types of statements in programs:

assignment: 47%
if: 23%
call: 15%
loop: 6%
goto: 3%
other: 7%

95% of assignments have 2 or fewer terms

57% of procedures have 2 or fewer variables
75% of calls have 2 or fewer parameters
etc

• RISC philosophy: create an instruction set

that lets you do the most common computations,
while maximising their efficiency

• To do this, throw away microprogramming, and

aim for instructions which execute in 1 cycle

• RISC chips have many features which are exportable

to contemporary CISC chips; also,
there are points of contention about design.

• There are also chips which seem to have both

CISC and RISC-like qualities.

B. Ross COSC 3p92 2

 History

IBM 370/168 VAX-11/780 Dorado iAPX-432

Year 1973 1978 1978 1982

No. of instructions 208 303 270 222
Control memory
size (Kbit) 420 480 136 64
Instr. size (bits) 16-48 16-456 8-24 6-321
Machine type register register stack stack

IBM 801 RISC I MIPS

Year 1980 1982 1983
No. of instructions 120 39 55
Control memory
size (Kbit) 0 0 0
Instr. size (bits) 32 32 32
Machine type register register register

B. Ross COSC 3p92 3

 History

The IBM 801 project (1975) was designed with the

following principles:

• choose an instruction set to be a good target for a

compiler
• provide a hardware engine that can execute its
instructions in one machine cycle
• design the storage hierarchy so that the control engine
does not have to wait for storage access
• base the entire system design on an optimizing
compiler

B. Ross COSC 3p92 4

 RISC vs CISC: characteristics

RISC CISC

1. simple instns taking 1. complex instns taking

1 cycle multiple cycles

2. only LOADs, STOREs 2. any instn. may access

access memory memory

3. designed around pipeline 3. designed around instn. set

4. instns. executed by h/w 4. instns interpreted by

microprogram

5. Fixed format instns 5. variable format instns

6. Few instns and modes 6. Many instns and modes

7. Complexity in the compiler 7. Complexity in the

microprogram

8. Multiple register sets 8. Single register set

B. Ross COSC 3p92 5

 RISC design

* Sacrifice everything to reduce the data path

cycle time.

* Microcode is not magic.

Five steps:

1. Find key operations in intended applications.

2. Design optimal data path for these operations.

3. Design instructions which perform these

operations on this data path.

4. add new instructions if they don't slow down

machine

5. repeat for other resources (cache, MMU,...)

B. Ross COSC 3p92 6

 Design issues

• single-cycle instructions

- key RISC characteristic

- rapid execution of simple instructions
- complex instns will require more compiled code

• only LOAD and STORE instns access memory

- permits pipelining efficiency

- not as many addressing modes

8.5

• maximal pipelining

- permits n instructions in n cycles

8.6

B. Ross COSC 3p92 7

 • pipelining (cont)

- Problems:
(i) memory accesses take 2 cycles
(ii) jumps ruin pipeline

- solutions:
For (i): - hardware interlock (wait)
- use incorrect register (means that
compiler needs to correct situation)

For (ii): need to optimise pipeline (instruction

order) at compile time.

• No Microcode

- eliminate interpretation, max. data path efficien.

- frees ALOT of chip space

• Fixed format instructions

- simple to decode

8.7

B. Ross COSC 3p92 8

 • Reduced instruction set

- because of simple instruction format

- with RISC I, offset can double as operand,
yielding 3 operand instructions.
- to effect complex addressing, need to generate
code to explicitly construct the addressing

• More compile-time complexity

- compiler technology is the reason that RISC

technology is feasible
- compiled code is executed directly, so compiler
must account for delayed instructions, register
usage,...
- lack of sophisticated instructions adds compiler
complexity (eg. Multiply)

• Multiple register sets

- RISC chips have lots of registers (100's!)

- techniques for organising them

B. Ross COSC 3p92 9

 Register Usage

• need to maximize pipeline, minimise memory access

• memory traffic in CISC is largely caused during

procedure calling

• RISC organises registers to minimise (remove)

memory accesses during procedure calls

- overlapping register window organisation

8.8

B. Ross COSC 3p92 10

 • CWP - current window pointer

• output and input register sets double up in

usage during procedure calls

• No stack needed UNLESS

- too many parameters

- parameters are too large in value

- too many nested calls cause all registers to be

used

... in which case standard stack techniques are used.

Remember: most programs are simple!

• Philosophical point:

Registers vs Memory
?

B. Ross COSC 3p92 11

 RISC vs CISC

• benchmarking computers is difficult

- effects of hardware organisation

(I/O, memory mgmt, ...)

- different chip technologies: ECL vs MOS

- operating system

- language effects: C vs Prolog vs COBOL vs ...

- type of program: recursive vs iterative

• Overlapping register windows:

- not part of MIPS chip

- could it be exported to CISC chips too?

B. Ross COSC 3p92 12

 CISC vs RISC
• compiler writing for RISC
eg. UltraSparc: instn after a jump in the pipeline
is executed before jump taken (Because instn to pre-fetch
at jump addr isn’t known until jump addr decoded)

• Delayed JUMP

100 LOAD X, A 100 LOAD X, A

101 ADD 1, A 101 ADD 1, A
102 JUMP 105 102 JUMP 106
103 ADD A, B 103 NO-OP
104 SUB C, B 104 ADD A, B
105 STORE A, Z 105 SUB C, B
106 106 STORE A, Z

Normal Branch Delayed Branch

00 LOAD X, A
101 JUMP 105
102 ADD 1, A
103 ADD A, B
104 SUB C, B
105 STORE A, Z
106

B. Ross COSC 3p92 Optimized Delayed Branch

13
 RISC compilers

• compilers need to acct for:

- memory delays
- jump delays
- register allocation
- simple instruction set

• RISC compilers need to make the best use of

registers
- preferable to use all the regs in a single window
(and not memory)

• optimising compilers can do data flow analysis

on programs to see when variables are "active"

B. Ross COSC 3p92 14

 Example 1: Pentium 4 (CISC)

• Recall:
– instruction formats [5.13]
– addressing modes [5.26]
• Instruction set: [5.33]
• CISC instruction set
– design determined for back-compatability
– superscalar microprocessor tries to “deconstruct”
CISC instns into pipelineable microinstructions
– erratic variants for instn type, register usage,
addressing modes
– [reference pages]

Example 2: Intel 8051

• Simple CISC instn set

• standard data movement, arithmetic
• powerful bit manipulation instructions

B. Ross COSC 3p92 15

 Example 3: UltraSparc III

• Recall: formats [5.14]

– addressing: either immediate or register
– only load, store access memory
• [5.34]

B. Ross COSC 3p92 16

 Example 4: MIPS R4000

• Microprocessor without Interlocking Pipe Stages

• similarities with UltraSPARC:

- 64 bit design
- LOAD/STORE architecture
- 2^64 byte-addressable memory
- paging, coprocessors, ...

• some differences:

- configurable to either Big- or Little-endian

(byte ordering in words)
- no register file or register windows
- no condition codes: results of tests saved in regs
- 8 stage pipeline

• Generally, MIPS does not give as orthogonal an

instruction set to programmer as SPARC, for
hardware efficiency sake.

B. Ross COSC 3p92 17

 • No window file:

pro: - with saved space, can fit MMU, cache

controller, MUL/DIV on chip
- removes overhead of saving 500 regs when
multitasking
- registers not fixed in purpose
con: - more (software) overhead in procedure
calling

B. Ross COSC 3p92 18

 Summary

• Pentium 4:
– 2-address, 32-bit CISC
– irregular
– back-compatible
• UltraSPARC
– 3-address, 64-bit RISC
– 128-bit bus
– somewhat complex formats
• Intel 8051
– simple CISC instns
– good bit manipulation
– 4 register sets for efficient interrupt processing
• MIPS
– another 64-bit RISC
SPARC vs. MIPS

orthogonal instns optimised H/W

register windows none

software MUL/DIV hardware MUL/DIV

condition codes none

B. Ross COSC 3p92 19