Timer /counter mode control register (TMOD) (SFR-89H)

B7 B6 B5 B4 B3 B2 B1 B0

GATE C/T M1 M0 GATE C/T M1 M0

GATE Gating control If 1, timer enabled only when INT0/INT1 high & run bit TR enabled in
TCON register
If 0, timer runs when TR enabled

C/T Counter/timer selector Mode select bit ; 1 –counter ,0-counter

M1 M0 Mode select bits To select among 4 modes

0 0 Mode 0 8 bit timer

0 1 Mode 1 16 bit timer
1 0 Mode 2 Autoreload mode 8 bit timer /counter;lower byte
increment and overflow caused reload by higher byte
1 1 Mode 3 Timer 1 hold count; timer 0 - 2 , 8 bit registers
 Timer units
• 2 nos 16 bit timers in timer/event counting mode –T0 ,T1

• Timer mode-timer register incremented each m/c;

- increment rate fx 1/12

• Counter mode-timer register incremented for 1 to 0 transition at the ext. port

pin(T0-P3.4 & T1-P3.5) sampled during S5P2 of every m/c cycle .
-Used as event counter

- Count updated only in S3P1 of the m/c cycle following the one in which transition
detected ie.
- Minimum 2 m/c cycles to identify 1 to 0

-so max counting frequency in counter mode – f/24

 Timer /counter mode control register (TMOD) (SFR-89H)
B7 B6 B5 B4 B3 B2 B1 B0

GATE C/T M1 M0 GATE C/T M1 M0

GATE Gating control If 1, timer enabled only when INT0/INT1 high & run bit TR enabled in
TCON register
If 0, timer runs when TR enabled

C/T Counter/timer selector Mode select bit ; 1 –counter ,0-timer

M1 M0 Mode select bits To select among 4 modes

0 0 Mode 0 8 bit timer

0 1 Mode 1 16 bit timer
1 0 Mode 2 Autoreload mode 8 bit timer /counter;lower byte
increment and overflow caused reload by higher byte
1 1 Mode 3 Timer 1 hold count; timer 0 - 2 , 8 bit registers
T0- mode 0
 Timer/counter mode 0
• 13 bit timer/counter- 8 bits of TH0 and lower 5 bits of TL0 for T0 and TH1 ,TL1
for T1
• Upper 8 bits TH0/TH1 to store count and lower 5 bits of TL0/TL1 as prescaler to
divide the i/p frequency by 32 .TH0 increments at freq. f/32
• For timer clock is internal and for counter ext clock given through To/T1 i/p
• Select bits are set in TCON

• If timer overflows TF0 flag in TCON set

-If timer 0 interrupt in enabled state, T0 interrupt occurs and vectored to its vector
address
TH0/TH1 and TF0 cleared TL0/TL1

B7 B6 B5 B4 B3 B2 B1 B0 B4 B3 B2 B1 B0
T0-mode-1
 Timer/counter -mode 1
• Timer register-16 bit wide

• Mode selection by C/T of TMOD

• TR0/TR1 –timer run control

• Overflow causes TFO set and timer 0 interrupt occurs

• Vectoring clears TF0 flag

T0-mode 2
 Timer mode 2
• Auto-reload 8 bit timer/counter T0 & T1
• TL0- timer/counter increments if TR0 in TCON set
-TF0 in TCON is set if TL0 overflows and reloaded from TH0
-if T0 interrupt is enabled , vectoring to related
address occurs and TF0 cleared
T1 operation –similar
T0-mode 3
 Mode 3
• 2 separate 8 bit timer/counters TL0 as T0 & TH0 as
T1
• TH0 –only timer , TL0-timer/counter
• Timer1 just holds its count and no function in mode
3 but can be turned on and off in mode 3 so as to
run in mode 0,1, or 2
Timer/counter control logic
Timer/counter control register TCON (SFR-88H)
TCON
Mode 0