6.

1 Memory & Programmable Logic Device Definitions

Chap.6
1

 Memory
 a collection of cells capable of storing binary information
 memory contains electronic circuits for storing & retrieving info

 a digital computer
 consist of three major units
 processing unit (registers + combinational logic)
 memory unit
 input-output unit
6.1 Memory & Programmable Logic Device Definitions
Chap.6
2

 two types of memories

 RAM (Random-Access Memory)
 can perform both read & write operation
 ROM (Read-Only Memory)
 can perform only the read operation (cannot write)
 the existing information cannot be altered
 a programmable logic device (PLD)

(programming: a H/W procedure that specifies the bits

that are inserted into the H/W configuration of the device)

 Programmable Logic Device (PLD)

 ROM, PLA, PAL, CPLD, & FPGA
 IC with internal logic gates (connected by a programmable process)
 initial state: all the fuses are intact
 programming by blowing those fuses along the paths
6.2 Random-Access Memory (RAM) Chap.6
3

 memory cells can be accessed for information transfer to o

r from any desired random location
 with access taking the same time regardless of the location
 random-access memory
(cf) serial memory: magnetic disk, tape

 word : binary information in groups of bits in a memory unit

 byte : a group of 8 bits
6.2 Random-Access Memory (RAM) Chap.6
4

 configuration:
 data input and output lines, address selection lines, & control lines

 k address lines: specify the particular word

 address range: 0 to 2k-1
 2k = m (m: total number of words)
6.2 Random-Access Memory (RAM) Chap.6
5

(ex) a memory unit w/ 1K words of 16 bits each

 1024 x 2 bytes = 2K bytes
 decimal address: 0 to 1023
 address: 10 bits; data: 16 bits
 6.2 Random-Access Memory (RAM) Chap.6
6

 Write & Read Operations

 steps of write operation
1) Apply the binary address to the address lines
2) Apply the data bits to the data input lines
3) Activate the Write input
 steps of read operation
1) Apply the binary address to the address lines
2) Activate the Read input
 control lines
 read & write
 memory select (or chip select) & operation (read/write)
 6.2 Random-Access Memory (RAM) Chap.6
7

 Timing Waveforms
 operation of the memory unit is controlled by an external device (CPU)
 CPU is usually synchronized with its own clock pulses
(memory doesn't employ internal clock pulses)
 Access time of a memory read operation
 the maximum time from the application of the address t
o the appearance of the data at the Data Output
 Write cycle time
 the maximum time from the application of the address t
o the completion to store a word
 CPU must provide the memory control signals to synchronize its intern
al clocked operations with read/write operations of the memory
 50MHz (= 20ns clock pulse)

6.2 Random-Access Memory (RAM) Chap.6

8

write cycle time

access time
 6.2 Random-Access Memory (RAM) Chap.6
9

 Properties of Memory
 Static RAM (SRAM)
 consist of internal latches that store the binary info
 stored info remains valid as long as power is applied
 easier to use, shorter read and write cycles
 Dynamic RAM (DRAM)
 store information in the form of electric charges
 capacitors are provided inside the chip by MOS transistors
 the capacitors must be periodically recharged by refreshing
 reduced power consumption, larger storage capacity
 Volatile
 lose stored information when power is turned off

(ex) RAM (static or dynamic)

(cf) non-volatile
(ex) magnetic disk, ROM
 6.3 RAM Integrated Circuits Chap.6
10

 Internal Structure
 a RAM chip of m words & n bits per word consists of m x n binary storage
cells, and decoders

 static RAM

 Select = 0, the stored content is held & C=0 & C'=0 Select = 1, the stor
ed content is determined by B & B', C is the stored value & C' is
its complement
6.3 RAM Integrated Circuits Chap.6
11

 RAM Bit
Slice Model
6.3 RAM Integrated Circuits Chap.6
12

 16 x 1 RAM Chip
 4 address inputs for
the 16 one-bit words

 Signals
Data Input,
Data Output,
Read/Write',
Chip Select

 4-to-16 line decoder

 6.3 RAM Integrated Circuits Chap.6
13

 Three-state Buffer
 have three distinct states
 logic-0, logic-1, high-impedance (Hi-Z) state
 Hi-Z state: open circuit,

(the output appears to be disconnected)

 ENABLE input (EN)

Three-state Buffer
 6.3 RAM Integrated Circuits Chap.6
14

 Form a multiplexed output line

 truth table (in shaded area) is a 2-way multiplexer with S

 6.3 RAM Integrated Circuits Chap.6
15

 Coincident Selection
 A decoder with k inputs & 2k outputs requires
2k AND gates with k inputs per gate
 employ 2 decoders to reduce the total number of gates
 Coincident Selection'

 use 2 k/2-input decoders instead of 1 k-input decoder

 one controls the word select lines,
 the other controls the bit select lines

 two dimensional matrix selection scheme

Row select & Column select
6.3 RAM Integrated Circuits Chap.6
16

 16 x 1 RAM chip
 4 RAM bit slice of
4 bits each
(total 16 RAM cells)

 two 2-to-4 line deco

ders
 one for 2 MSBs
 one for 2 LSBs
 Chap.6
17

(cf) 8 x 2 RAM chip

(8 words of 2 bi
ts each)
3 address bits
 two are handled
by the r
ow decoder
 column decoder
has only one add
ress bit & pro
duces 2 column s
elect lines
 6.3 RAM Integrated Circuits Chap.6
18

(Ex) 32K x 8 RAM

 a total of 256K bits (= 218)
 square root of 256K is 29
 first 9 bits fed to the row decoder
 remaining 6 bits to the column decoder

 without coincident selection,

the single decoder has 15 inputs & 32,768 outputs
(32,800 gates)
 with coincident selection,
one 9-to-512 decoder and one 6-to-64 line decoder
(608 gates)
 6.4 Array of RAM ICs Chap.6
19

 if required memory size is larger than the capacity of one chip,

combine a number of chips in an array
 capacity of memory
 the number of words & the number of bits per word

 64K x 8 RAM chip

 16 address lines, 8 input & 8 output lines
 CS (chip select), R/W' inputs
6.4 Array of
Chap.6
20

RAM ICs

 construct 256K x 8 RAM

 four 64K x 8 RAM chips
 requires 18-bit address
lines
 2 MSBs are applied to
a 2 x 4 decoder,
 4 outputs are applied to
the CS inputs of th
e four chips
 6.4 Array of RAM ICs Chap.6
21

 Form a 64K x 16 memory

 16 data input & output lines are split between the two chips
 6.5 Programmable Logic Technologies Chap.6
22

 Five programmable logic devides (PLDs)

 ROM, PLA, PAL, CPLD, & FPGA

 Programming technologies
 fuse
 oldest of the programming technologies
 each of programmable points consists of a connection, f
ormed by a fuse
 2 connection states, CLOSED & OPEN
 mask programming
 by semiconductor manufacturer
 antifuse
 the opposite of a fuse
 static RAM bit
 drive the gate of an MOS transistor at the programming point
 6.5 Programmable Logic Technologies Chap.6
23

 use of programming technologies

 control connections
 implement logic by using lookup tables
 input: address inputs for reading the SRAM
 output: stored values for the addressed word
 control transistor switching
 6.6 Read-Only Memory Chap.6
24

 a memory device in which permanent binary info is stored

 once a pattern is established, it stays even when power is off
 consist of k address inputs and n data outputs

 input: address for the memory;

output: data bits of the stored word, selected by the address
(no data input lines !!)
 k address input lines are needed to specify 2k words
 6.6 Read-Only Memory Chap.6
25

(ex) a 32 x 8 ROM

 the unit consists of 32 words of 8 bits each

 a 5 x 32 decoder (5 input lines)
 the internal binary storage of a ROM is specified by a truth table
6.6 Read-Only Memory Chap.6
26

(ex) the contents of a 32 x 8 ROM

programming the ROM

according to the truth table
 6.6 Read-Only Memory Chap.6
27

 Types of ROMs
 mask programming (ROM)
 fuse (PROM)
 erasable floating gate technology (EPROM)
 electrically erasable technology (EEPROM, E2PROM)

 Combinational Circuit Implementation

 a decoder generates the 2k minterms of the k input variables
 inserting OR gates to sum the minterms of Boolean functions
=> can generate any desired combinational circuit
 ROM essentially includes both decoder & OR gates
 ROM outputs can be programmed to represent the Boolean functions in a c
ombinational circuit
 ROM may be considered as a comb circuit with (8) outputs, each is a func
tion of the (5) input variables A7(I4,I3,I2,I1,I0) =  m(0,2,3,...,
29)
 widely used to implement complex combinational circuits directly
 6.6 Read-Only Memory Chap.6
28

Ex 6.1 Design a comb circuit using a

ROM

accepts a 3-bit number &

generates an output binary No. eq
ual to the square of the input No.

3 inputs & 6 outputs but B0 = A0; B1 = 1;

 only need 4 outputs  ROM must be 8 x 4
 6.6 Read-Only Memory Chap.6
29

 Programmable Logic Device

 an integrated circuit with an array of gates that are connected by prog
rammable fuses
 the gates in a PLD are divided into AND array & OR array to provide
and AND-OR sum of products implementation

 PROM
 a fixed AND array constructed as a decoder & programmable con
nections for the output OR gates
 implements Boolean functions in sum-of-minterms form

 PAL
 a programmable connection AND array & a fixed OR array
 AND gates are programmed to provide the product terms, which are
logically summed in each OR gate
 6.6 Read-Only Memory Chap.6
30

 PLA
 most flexible PLD
 both AND & OR arrays can be programmed
 product term in the AND array may be shared by any OR gate
to provide the required sum of products implementation

 advantage of using the PLD

 can be programmed to incorporate a complex logic function
within one IC
6.6 Read-Only Memory Chap.6
31
6.7 Programmable Logic Array (PLA) Chap.6
32

 PLA is similar to the PROM in concept

 but the PLA doesn't provide full decoding of the variables &
doesn't generate all the minterms
 decoder is replaced by an array of AND gates t
o generate any product term of the input variables
 the product terms are then connected to OR gates t
o provide the sum of products

 internal logic of a PLA w/ 3 inputs & 2 outputs

 each input goes through a buffer and an inverter
 connected through fuses to the inputs of each AND gate
 output of AND gates are connected by fuses to OR gate
 output of OR gates goes to an XOR gate, wher
e the other input can be programmed to receive a signal
6.7 Programmable Logic Array (PLA) Chap.6
33

F1 = AB' + AC + A'BC'; F2' = AC + BC

 6.7 Programmable Logic Array (PLA) Chap.6
34

the fuse map of a PLA in a tabu

lar form;
consists of 3 sections
list of the product terms
the required paths between inp
uts & AND gates
the path between the AND & O
R gates

a careful investigation must be undertaken to reduce the number of distinct product term

s (since PLA has a finite number of AND gates)

 simplify each Boolean function to a minimum No of terms
 obtain both the true & complement of the function
 select a comb that gives a minimum No of product terms
 6.7 Programmable Logic Array (PLA) Chap.6
35

Ex 6.2 Implement the following f

unctions with a PLA
F1(A,B,C) =  m(0,1,2,4);
F2(A,B,C) =  m(0,5,6,7)

1) true & complement of the func

tions are simplified in sum of p
roducts
2) select a combination that gives
a minimum No of product term
s
F1 = (AB +AC +BC)';
F2 = AB + AC + A'B'C'
 Chap.6
36

6.8
Programmable
Array Logic
(PAL)

 PLD with a fixed OR array & progra

mmable AND array
 easier to program
(only AND gates are programma
ble),
 not flexible as the PLA
 logic configuration of a typical PAL
 4 inputs & 4 outputs
6.8 Programmable Array Logic (PAL) Chap.6
37

 4 section in the unit,

 each composed of a 3-wide AND-OR array

 3 programmable AND gates in each section

 output terminals are sometimes bidirectional

 F/Fs are often included in a PAL device

 outputs of F/F are fed back through a buffer-inverter gate

(sequential circuits !!)

 in designing with a PAL,

 the Boolean functions must be simplified to fit into each section
 a product term cannot be shared
 number of product terms in each section is fixed

 may be necessary to use 2 sections to implement 1 function

6.8 Programmable Array Logic (PAL) Chap.6
38

(Ex) W(A,B,C,D) =  m(2,12,13);

X(A,B,C,D) =  m(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) =  m(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) =  m(1,2,8,12,13)

after simplification
W= ABC' + A'B'CD';
X = A + BCD;
Y = A'B + CD + B'D';
Z = ABC' + A'B'CD' + AC'D' + A'B'C'D
= W + AC'D' + A'B'C'D;
 6.8 Programmable Array Logic (PAL) Chap.6
39

- PAL programmable table

W = ABC' + A'B'CD'; X = A + BCD;
Y = A'B + CD + B'D'; Z = ABC' + A'B'CD' + AC'D' + A'B'C'D
= W + AC'D' + A'B'C'D;
Chap.6
40