Chapter #8: Finite State Machine Design

Chapter #8: Finite State Machine Design
No. 8-1
Motivatio
n
Counters: Sequential Circuits where State = Output
Generalizes to Finite State Machines:

Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" logic
Application of Sequential Logic Design Techniques

Word Problems
Mapping into formal representations of FSM behavior
Case Studies
No. 8-2
Chapter Overview
Concept of the State Machine
Partitioning into Datapath and Control
When Inputs are Sampled and Outputs Asserted
Basic Design Approach
Six Step Design Process
Alternative State Machine Representations
State Diagram, ASM Notation, VHDL, ABEL Description Language
Moore and Mealy Machines
Definitions, Implementation Examples
Word Problems
Case Studies
No. 8-3
Concept of the State
Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Reset Present State Input Next State Output

Even 0 Even 0
0 Even 1 Odd 0
Even
[0] Odd 0 Odd 1
Odd 1 Even 1
1 1 Symbolic State Transition Table
Odd
[1] Present State Input Next State Output
0
0 0 0 0
0 1 1 0
1 0 1 1
State 1 1 0 1
Diagram
Encoded State Transition Table
No. 8-5
Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
Input Output
NS T Q
Input CLK
D Q
PS/Output
CLK Q
Q R
R
\Reset \Reset
D FF Implementation T FF Implementation
Input 1 0 0 1 1 0 1 0 1 1 1 0
Clk
Output 1 1 1 0 1 1 0 0 1 0 1 1
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

No. 8-6
Concept of State
Machine
Timing:
When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
Clocking event causes state/outputs to transition, based on inputs
For set-up/hold time considerations:
Inputs should be stable before clocking event
After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately

Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately

sync. counter clear: effective at next clock event
No. 8-7
Concept of State
Machine
Example: Positive Edge Triggered Synchronous System
State T ime On rising edge, inputs sampled

outputs, next state computed
After propagation delay, outputs and

next state become stable
Clock
Immediate Outputs:
affect datapath immediately
Inputs could cause inputs from datapath to change
Delayed Outputs:
take effect on next clock edge
Outputs propagation delays must exceed hold times
No. 8-8
Machine
Communicating State Machines
One machine's output is another machine's input
X
CLK
FSM 1 FSM 2
Y
FSM 1 A A B
X
Y=0 X=0
Y=0 X=0
A C FSM 2 C D D
[1] [0]
X=1 Y
Y=1
X=1
B D
Y=0,1 [0] X=0 [1]
Fragment state diagrams

Initial inputs/outputs: X = 0, Y = 0
No. 8-9
Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment (or encoding)
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3~6 covered later (Chap. 9);

5 and 6 generalized from the counter design procedure
No. 8-10
Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes (10 cents), nickels (5 cents)
no change
Step 1. Understand the problem:

Draw a picture!
Block Diagram N
Coin
Vending Open Gum
Sensor D Machine Release
Reset FSM Mechanism
Clk
No. 8-11
Vending Machine
Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:

three nickels
nickel, dime
dime, nickel Reset
two dimes S0
two nickels, dime
N D
Draw state diagram:
S1 S2
Inputs: N, D, reset
Output: open N D
D N
S3 S4 S5 S6
[open] [open] [open]
N D
S7 S8
[open] [open]
No. 8-12
Vending Machine
Example
Step 3: State Minimization
Present Inputs Next Output
Reset
0¢
State D N State Open
0¢ 0 0 0¢ 0
N 0 1 5¢ 0
5¢
1 0 10¢ 0
D 1 1 X X
5¢ 0 0 5¢ 0
N 0 1 10¢ 0
10¢ 1 0 15¢ 0
D 1 1 X X
N, D 10¢ 0 0 10¢ 0
15¢
0 1 15¢ 0
1 0 15¢ 0
[open]
1 1 X X
15¢ X X 15¢ 1
reuse states
whenever Symbolic State Table
possible
No. 8-13
Vending Machine
Example
Step 4: State Encoding
Present State Inputs Next State Output
Q1 Q0 D N D 1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X
No. 8-14
Parity Checker Example
Step 5. Choose FFs for implementation
D FF easiest to use
D1 D0 Open
Q1
D D1 D Q Q1
Q0 CLK \ Q1
RQ
N
\reset
D1 = Q1 + D + Q0 N
N
\ Q0 OPEN
D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q0
\N
D0 D Q0
Q1
Q OPEN = Q1 Q0
CLK \ Q0
N RQ
Q1 \reset
D
8 Gates
No. 8-15
Parity Checker Example
Step 5. Choosing FF for Implementation

J-K FF
Present State Inputs Next State J1 K1 J0 K 0

Q1 Q0 D N D1 D0
0 0 0 0 0 0 0 X 0 X
0 1 0 1 0 X 1 X
1 0 1 0 1 X 0 X
1 1 X X X X X X
0 1 0 0 0 1 0 X X 0
0 1 1 0 1 X X 1
1 0 1 1 1 X X 0
1 1 X X X X X X
1 0 0 0 1 0 X 0 0 X
0 1 1 1 X 0 1 X
1 0 1 1 X 0 1 X
1 1 X X X X X X
1 1 0 0 1 1 X 0 X 0
0 1 1 1 X 0 X 0
1 0 1 1 X 0 X 0
1 1 X X X X X X
Remapped encoded state transition table

No. 8-16
Vending Machine
Example
Implementation:
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
N
Q0 J Q Q1
D \ Q1
CLK K Q
\ Q0 R
N
OPEN
Q1
D Q0
J Q
\ Q1 CLK
\ Q0
KR Q
N
\reset 7 Gates
No. 8-17
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specified

sequence of actions based on input data
algorithm = sequencing + data manipulation
separation of control and data
Gradual shift towards program-like representations:
Algorithmic State Machine (ASM) Notation
Hardware Description Languages (e.g., VHDL)
No. 8-18
Algorithmic State Machine (ASM) Notation
Three Primitive Elements:
State Box
Decision Box State

Entry Path
Output Box State Code

* ***
State Machine in one state State State Box
block per state time Name
State ASM
Output List
Single Entry Point T F
Block
Condition
Unambiguous Exit Path

for each combination Condition Output
Box
of inputs Box
Conditional
Output List
Outputs asserted high (.H)
or low (.L); Immediate (I) Exits to
other ASM Blocks
or delayed til next clock
No. 8-19
ASM Notation
Condition Boxes:
Ordering has no effect on final outcome
Equivalent ASM charts:

A exits to B on (I0 & I1 = 1) else exit to C
A 010 A 010
F F
I0 I1
T T
F F
I1 I0
T T
B C B C
No. 8-20
Example: Parity Checker
Input X, Output Z
Even 0
Nothing in output list implies Z not asserted
Z asserted in State Odd

F
X Symbolic State Table:
T
Present Next
Input State State Output
Odd 1 F Even Even
H.Z T Even Odd
F Odd Odd A
T Odd Even A
F T
X
Encoded State Table:
Present Next
Input State State Output
Trace
Tracepaths
pathstotoderive
derive 0 0 0 0
state transition tables
state transition tables 1 0 1 0
0 1 1 1
1 1 0 1
No. 8-21
ASM Chart for Vending Machine
0¢ 00 10¢ 10
T T
D D
F F
F F
N N
T T
5¢ 01 15¢ 11
H.Open
T F
N Reset
F T
F T
D 0¢
No. 8-22
Moore and Mealy Machine Design
Procedure
Definitions
State
Register
Moore Machine
Xi Combinational
Comb. Outputs are function
Logic for
Inputs Logic for
Outputs
solely of the current
Next State state
(Flip-flop Zk
Inputs) Outputs
Outputs change
Clock synchronously with
state changes
state
feedback
Zk
Mealy Machine
Xi
Inputs Combinational Outputs
Logic for Outputs depend on
Outputs and state AND inputs
Next State
Input change causes
State
Feedback
an immediate output
State Register Clock change
Asynchronous outputs
No. 8-23
Moore and Mealy
Machines
State Diagram Equivalents
N D + Reset
Moore Reset Reset/0
(N D + Reset)/0
Mealy
Machine 0¢ 0¢ Machine
[0]
Reset Reset/0
N N/0
5¢ 5¢
ND D N D/0 D/0
[0]
N N/0
10¢ 10¢
D D/1
[0] ND N D/0
N+D N+D/1
15¢ 15¢
[1] Reset Reset/1
Outputs are associated Outputs are associated

with State with Transitions
No. 8-24
Moore and Mealy
Machines
States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
Asserts its output 0
0 0/0
whenever at least two

1’s in sequence [0]
0/0 1/0
0 1
0 1
Same I/O behavior 1
1/1
[0]
Different # of states 1
2
[1] 1
S0 00 S0 0
IN
F F
IN
S1 T 01 S1
T 1
Equivalent
ASM Charts
IN F IN
F
S2 T 10 T
H.OUT H.OUT
T
IN
F
No. 8-25
Moore and Mealy
Machines
Timing Behavior of Moore Machines
Reverse engineer the following: why Moore ???
X J Q A Input X
C Output Z
X
KR Q \A State A, B (= Z)
\B
FFa
\Reset
Clk
X J Q Z
X C
KR Q \B
\A
FFb
\Reset
Two Techniques for Reverse Engineering:
Ad Hoc: Try input combinations to derive transition table
Formal: Derive next state/output functions by analyzing the circuit

No. 8-26
Moore and Mealy
Machines
Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
100
X
Clk
A
Z
\Reset
Reset X=1 X=0 X=1 X= 0 X=1 X= 0 X= 0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00
A B X A+ B+ Z
0 0 0 ? ? 0
1 1 1 0
0 1 0 0 0 1
Partially Derived
1 ? ? 1
State Transition 1 0 0 1 0 0
Table 1 0 1 0
1 1 0 1 1 1
1 1 0 1
No. 8-27
Moore and Mealy
Machines
Formal Reverse Engineering
Derive transition table from next state and output combinational
functions presented to the flipflops!
Ja = X Ka = X B Z=B
Jb = X Kb = X xor A
FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q

A+ = Ja A + Ka A = X A + (X + B) A
B+ = Jb B + Kb B = X B + (X A + X A) B
Next State K-Maps:
State 00, Input 0  State 00

State 01, Input 1  State 11
No. 8-28
Moore and Mealy
Machines
Complete ASM Chart for the Mystery Moore Machine
S0 00 S3 11
H.Z
0 1 0
X X
1
S1 01 S2 10
H.Z
0 1 1 0
X X
Note: All Outputs Associated With State Boxes

No Separate Output Boxes, Intrinsic in Moore Machines
No. 8-29
Moore and Mealy
Machines
Reverse Engineering a Mealy Machine
Clk
\A
X
A B
D Q J Q
DA C
\A \B
C \X
R Q KR Q
\Reset \Reset
A
DA \X
X
B
B Z
\X X
A
Input X, Output Z, State A, B

State register consists of D FF and J-K FF
No. 8-30
Moore and Mealy
Machine
Ad Hoc Method
Signal Trace of Input Sequence 101011:
100
X Note glitches
Clk
in Z!
A Outputs valid at
B following falling
clock edge
Z
\Reset
Reset X =1 X =0 X =1 X =0 X =1 X =1
AB =00 AB =00 AB =00 AB =01 AB =11 AB =10 AB =01
Z =0 Z =0 Z =0 Z =0 Z=1 Z =1 Z =0
A B X A+ B+ Z
0 0 0 0 1 0
Partially completed 1 0 0 0
state transition table 0 1 0 ? ? ?
based on the signal 1 1 1 0
trace 1 0 0 ? ? ?
1 0 1 1
1 1 0 1 0 1
1 ? ? ?
No. 8-31
Moore and Mealy
Machines
Formal Method
A+ = B (A + X) = A B + B X
B+ = Jb B + Kb B = (A xor X) B + X B
=ABX + ABX + BX
Z =AX + BX
Missing Transitions and Outputs:
State 01, Input 0 -> State 00, Output 1
State 10, Input 0 -> State 00, Output 0
A+ State 11, Input 1 -> State 11, Output 1
B+
No. 8-32
Moore and Mealy
Machines
ASM Chart for Mystery Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11
S0 00 S2 10
0
1 X
X
0 1
H. Z
H. Z S1 01 S3 11
H.Z
0 1 1
X X
0
NOTE: Some Outputs in Output Boxes as well as State Boxes

This is intrinsic in Mealy Machine implementation
No. 8-33
Moore and Mealy
Machines
Synchronous Mealy Machine
Clock
Xi Zk
Inputs Combinational
Outputs
Logic for
Outputs and
Next State
State Register Clock state

feedback
latched state AND outputs
avoids glitchy outputs!
No. 8-34
Finite State Machine Word
Problems
Mapping English Language Description to Formal Specifications
Four Case Studies:
Finite String Pattern Recognizer
Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
We will use state diagrams and ASM Charts
No. 8-35
Problems
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:

X: 00101010010
Z: 00010101000
X: 11011010010
Z: 00000001000
No. 8-36
Problems
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
Moore State Diagram

Reset signal places
FSM in S0
Outputs 1 Loops in State
No. 8-37
Problems
Exit conditions from state S3:
if next input is 0 then have …0100 (state S6)
if next input is 1 then have …0101 (state S2)
No. 8-38
Problems
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)

loop back to S4 if input is 1
No. 8-39
Problems
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)

S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)

S2 handles just this case!
Final State Diagram
No. 8-40
Problems
Review of Process:
Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences

to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions

like the specification
No. 8-41
Problems
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111

Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:

Mode Input M Current State Next State (Z2 Z1 Z0)
0 000 001
0 001 010
1 010 110
1 110 111
1 111 101
0 101 110
0 110 111
No. 8-42
Problems
Complex Counter
One state for each output combination
Add appropriate arcs for the mode control
S0 000
S1 001
H.Z 0
0 1
M
S2 010 S3 011
H.Z 1 H.Z 1
H.Z 0
0
M
1
M
1
0
S6 110
H.Z 2 S4 100
H.Z 1 H.Z 2
1
S7 111 M
H.Z 2 0
H.Z 1
H.Z 0 S5 101
H.Z 2
0 1 H.Z 0
M
0 1
M
No. 8-43
Problems
A busy highway is intersected by a little used farmroad. Detectors

C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
No. 8-44
Problems
Picture of Highway/Farmroad Intersection:
Farmroad
C
HL
FL
Highway
Highway
FL
HL C
Farmroad
No. 8-45
Problems
Tabulation of Inputs and Outputs:
Input Signal Description
reset place FSM in initial state
C detect vehicle on farmroad
TS short time interval expired
TL long time interval expired
Output Signal Description

HG, HY, HR assert green/yellow/red highway lights
FG, FY, FR assert green/yellow/red farmroad lights
ST start timing a short or long interval
Tabulation of Unique States: Some light configuration imply others

State Description
S0 Highway green (farmroad red)
S1 Highway yellow (farmroad red)
S2 Farmroad green (highway red)
S3 Farmroad yellow (highway red)
No. 8-46
Problems
Refinement of ASM Chart:
Start with basic sequencing and outputs:
S0 S3
H.HG H.HR
H.FR H.FY
S1 S2
H.HY H.HR
H.FR H.FG
No. 8-47
Problems
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C · TL
S0 S0
H.HG H.HG
H.FR H.FR
C · TL
0 0
TL TL • C
1 1
0
C H.ST
1
H.ST S1
H.HY
H.FR
S1
H.HY
H.FR
Equivalent ASM Chart Fragments

No. 8-48
Problems
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition
S1 S2
H.HY H.ST H.HR
H.FR H.FG
0 1
TS
No. 8-49
Problems
S2 Exit Condition: no car waiting OR long time interval expired
S0 S3
H.HG H.HR
H.FR H.ST H.FY
0 1 0
TL • C TS
H.ST H.ST
S1 S2
H.HY H.ST H.HR
H.FR H.FG
0 1 0
TS TL + C
1
Complete ASM Chart for Traffic Light Controller

No. 8-50
Problems
Compare with state diagram:
TL + C
Reset
S0: HG
S0
TL•C/ST TS/ST S1: HY
TS
S2: FG
S1 S3
TS S3: FY
TS/ST
TL + C/ST
S2
TL • C
Advantages of ASM Charts:
Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into

single Boolean condition for exit
Easier to understand the design as an algorithm

No. 8-51
Problems
"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:

how do you set the internal combination?
exactly when is the ERROR light asserted?
Make reasonable assumptions:

hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination
has been entered
Our design: registered combination plus error after full combination

No. 8-52
Problems
Understanding the problem: draw a block diagram
RESET
Operator Data ENTER UNLOCK

KEY-IN
Combination
Lock FSM ERROR
L0
Internal
Combination L1
L2
Inputs: Outputs:
Reset Unlock
Enter Error
Key-In
L0, L1, L2
No. 8-53
Problems
Enumeration of states:
what sequences lead to opening the door?

error conditions on a second pass
START state plus three key COMParison states
START
START entered on RESET
Exit START when ENTER is pressed

1
Reset
0
Enter
0
1
COMP0
N
Continue on if Key-In matches L0
KI = L0
Y
No. 8-54
Problems
COMP0 IDLE1
Path to unlock:
N 0
KI = L 0 Enter
Y 1
IDLE0 COMP2
Wait for
Enter Key press
0 N
Enter KI = L2
1 Y
COMP1 DONE
H.Unlock
N 0
Compare Key-IN KI = L1 Reset
Y 1
START
No. 8-55
Problems
Now consider error paths
Should follow a similar sequence as UNLOCK path, except

asserting ERROR at the end:
IDLE0' IDLE1' ERROR3

H.Error
0 0
Enter 0 Reset
Enter
1 1 1
ERROR1 ERROR2
START
COMP0 error exits to IDLE0'
COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3
No. 8-56
Finite State Machine Word Reset + Enter
Problems
Digital Combination Lock Reset
Start
Reset • Enter
Comp0
KI = L0 KI ° L0
Enter Enter
Idle0 Idle0'
Enter Enter
Comp1 Error1
Equivalent State Diagram KI ° L1
KI = L1
Enter
Enter
Idle1 Idle1'
Enter Enter
Comp2 Error2
KI = L2 KI ° L2
Reset Reset
Done Error3
[Unlock] [Error]
Reset Reset
Start Start
No. 8-57
Chapter Review
Basic Timing Behavior an FSM
when are inputs sampled, next state/outputs transition and stabilize
Moore and Mealy (Async and Sync) machine organizations
outputs = F(state) vs. outputs = F(state, inputs)
First Two Steps of the Six Step Procedure for FSM Design
understanding the problem
abstract representation of the FSM
Abstract Representations of an FSM

ASM Charts
Word Problems
understand I/O behavior; draw diagrams
enumerate states for the "goal"; expand with error conditions
reuse states whenever possible
No. 8-58

Chapter #8: Finite State Machine Design

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Chapter #8: Finite State Machine Design

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Chapter #8: Finite State Machine Design

Counters: Sequential Circuits where State = Output

Generalizes to Finite State Machines:

Application of Sequential Logic Design Techniques

Partitioning into Datapath and Control

When Inputs are Sampled and Outputs Asserted

Basic Design Approach

Six Step Design Process

Alternative State Machine Representations

State Diagram, ASM Notation, VHDL, ABEL Description Language

Moore and Mealy Machines

Definitions, Implementation Examples

Reset Present State Input Next State Output

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

State Time: Time between clocking events

Clocking event causes state/outputs to transition, based on inputs

For set-up/hold time considerations:

Inputs should be stable before clocking event

After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediately

E.g., tri-state enable: effective immediately

State T ime On rising edge, inputs sampled

After propagation delay, outputs and

Fragment state diagrams

2. Obtain an abstract specification of the FSM

3. Perform a state minimization

4. Perform state assignment (or encoding)

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3~6 covered later (Chap. 9);

single coin slot for dimes (10 cents), nickels (5 cents)

Step 1. Understand the problem:

Tabulate typical input sequences:

Step 5. Choosing FF for Implementation

Present State Inputs Next State J1 K1 J0 K 0

Remapped encoded state transition table

Not suitable for gradual refinement of finite state machine

Do not obviously describe an algorithm: that is, well specified

algorithm = sequencing + data manipulation

separation of control and data

Gradual shift towards program-like representations:

Algorithmic State Machine (ASM) Notation

Hardware Description Languages (e.g., VHDL)

Decision Box State

Output Box State Code

Unambiguous Exit Path

Equivalent ASM charts:

Z asserted in State Odd

[1] Reset Reset/1

Outputs are associated Outputs are associated

whenever at least two

Two Techniques for Reverse Engineering:

Ad Hoc: Try input combinations to derive transition table

Formal: Derive next state/output functions by analyzing the circuit

FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q

State 00, Input 0  State 00

Note: All Outputs Associated With State Boxes

Input X, Output Z, State A, B

NOTE: Some Outputs in Output Boxes as well as State Boxes

State Register Clock state

latched state AND outputs

avoids glitchy outputs!