DFT

(Design for testability)

ATPG

-JAGANATH SINGH
 ATPG Definition
 Proper inputs tool will generate by performing the fault simulation based on the algorithm
tool will generate the pattern

 Automatic test equipment is a computer control equipment used in the production of testing
of ICS ( Both at the wafer level packaged devices and PCBs)

 Test patterns are applied to the CUT and the output responses are compared to stored response
for the fault free circuit

 Generating effective test patterns efficiently for a Digital circuit the goal of any automated
test pattern generation system
Inputs & Outputs for ATPG
INPUTS OF ATPG
1.Library files
2.Netlist ( Scan inserted/Scan Compressed)
3.ATPG setup file->Do file->Test Proc file
4. Log files
5. Run file
6. SDC file

OUTPUTS OF ATPG
1. Testbench
Chain test (SHIFT & CAPTURE) for serial & parallel simulation
2. Cycle & Pattern count file.
3. AU fault list
4. Coverage Report files
5. Scan Chains & scan group files.
 INPUTS
Libraries: contains information of gates, flops,model reference name in the form of a code

Scan +compressed netlist: contains scan & compression inserted logic

ATPG setup files: contains the setup information for ATPG

 ATPG Dofile: has scan info, chain length from SI to SO

 ATPG testproc files: contains timescale, setup procedure, load/unload, shift, capture, sequential procedure
info, edt clock, edt update, edt bypass information etc

SDC files: Synopsis Delay Constraints, contains timing information like false path, multicycle path info, etc

Log files: contains all the report information

Run files: contains the path of the netlist, library to execute the operation
 OUTPUTS
Testbenches: chain test (Shift) and shift & capture testbenches for serial & parallel simulations. These are
the inputs for simulations

Cycle counts & Pattern counts: contains how many flops are present per chain info & how many patterns
generated after ATPG

Coverage reports: contains fault coverage & test coverage info

AU fault list files: contains the info of ATPG untestable faults and why the coverage is lose

Scan chain & Scan group files: contains number of scan chains and scan chain group information
ATPG Faults Model

 Stuck at Fault

 Transition Fault

 Path delay Fault

 IDDQ fault
Stuck at Fault

 stuck at fault is a operation present at input and output side.

 stuck at fault models perform get the controllability and observability of the design.

 stuck at fault is running at low frequency for the shift and capture
 Transition Fault
 A transition at any node means that the effect of any transition from 0>1(slow to rise) or 1>0 (slow to fall)
will not reaches at primary output or scan flop output with in the stipulated time
Slow to rise: when the system is at max freq, it is unable to produce transition from 0 to 1. OR gate is used for
0 to 1 transition.
Slow to fall: when the system is at max freq, it fails to transit from 1 to 0. AND gate is used for 1 to 0
transition.
 TRANSITION DELAY FAULT TESTING
 APPROACH
There are 2 approaches to test transition delay:
1. Launch On Shift(LOS)
2. Launch On Capture(LOC)
 LAUNCH ON SHIFT(LOS): Here the data is launched from shift path ie, when SE=1 and capture is done
from combo path ie, when SE=0
 But SE changes immediately, that need to be taken care or else it reaches metastable. So to add delay for
SE to change from 1 to 0 insert pipeline registers which adds delay ie, Launch on extra shift pulse.
 Coverage is more
 Less patterns
 STA is difficult to meet
LAUNCH ON CAPTURE(LOC): Here data is launched and captured from capture path
itself ie, D path
 Both launch & capture happens when SE=0. So no need od pipeline insertion required
 But SE remains zero for both launch & capture, hence coverage is lost
 Patterns is more because the patterns comes from combo path
 STA is easy to meet
 Path delay Fault
 Path delay fault model defects in the circuit path

 Testing the combined delay through all the gates of the specific path(critical path)

 Propagation delay of all paths in the circuits must be less than one clock cycle
IDDQ fault
 IDDQ testing is a method for testing CMOS integrated circuits for the presence of
manufacturing faults.
 This has the advantage of checking the chip for many possible faults with one
measurement.
 Another advantage is that it may catch faults that are not found by conventional stuck-at
fault test vectors.
 ATPG Faults Classes
Fault classes means it is a set of class where we can define the fault models

There are two type of Faults classes

 Testable
It could able to detect fault while performing the fault model is called as testable faults
 Untestable
Untestable (UT) faults are faults for which no pattern can exist to either detect or possible-detect them. The
tools acquire some knowledge of faults prior to ATPG, they classify certain unused, tied, or blocked faults
before ATPG runs.
ATPG Faults classes
 Untestable
 Redundant fault
 Tide Fault
 Blocked
 Unused
 Testable
 Detectable DI (Detectable Implication)
DS (Detectable simulation)
Pos Detectable Testable
 Possible Detectable Pos Detectable Untestable
• Backboxes
• Pin constraints
• Insufficient Seq depth
 ATPG Untestable • Analog boxes
Uncontrollable • Tide to unknown logic
 Undetectable Unobservable • Non scan elements
 Untestable
 Redundant fault:
The redundant fault class includes faults the test generator considers undetectable. After the test pattern
generator exhausts all patterns, it performs a special analysis to verify that the fault is undetectable under
any conditions

 Tide Fault:
The tied fault class includes faults on gates where the point of the fault is tied to a value identical to the
fault stuck value.• Because tied values propagate, the tied circuitry at A causes tied faults at A, B, C, and
D.
 Blocked:
The blocked fault class includes faults on circuitry for which tied logic blocks all paths to an
observable point.• Tied faults and blocked faults can be equivalent faults.

 Unused:
The unused fault class includes all faults on circuitry unconnected to any circuit observation point
and faults on floating primary outputs
Testable
 Detectable:

The detected fault class includes all faults that the ATPG process identifies as detected. The
detected fault class contains two sub classes ,

Det simulation (DS) - faults detected when the tool performs fault simulation. Det
implication (DI) - faults detected when the tool performs learning analysis.

 Possible Detectable:

The posdet, or possible-detected, fault class includes all faults that fault simulation identifies
as possible-detected but not hard detected. A possible-detected fault results from a 0-X or 1-
Xdifference at an observation point. The posdet class contains two subclasses.
 ATPG Untestable:

Untestable (UT) faults are faults for which no pattern can exist to either detect or possible-detect them.
Untestable faults cannot cause functional failures, so the tools exclude them when calculating test coverage

 Undetectable:

The undetected fault class includes undetected faults that cannot be proven untestable or ATPG untestable.
The undetected class contains two subclasses:

uncontrolled (UC) - undetected faults, which during pattern simulation, never achieve the value at the point
of the fault required for fault detection-that is, they are uncontrollable.

unobserved (UO) - faults whose effects do not propagate to an observable point.

Types of ATPG
 Combinational ATPG
 Sequential ATPG
 Multiload ATPG

 Combinational ATPG (Req 1clk cycle)

The combinational ATPG method allows testing the individual nodes (or Flipflop) of the logic
circuit without being concerned with the operation of the overall circuit

 Sequential ATPG (Req 2clk cycle)

sequential circuit ATPG searches for a sequence of test vectors to detect a particular fault
through the space of all possible test vector sequence

 Multiload ATPG (Req Min 3clk cycle)

Combination of both sequential & combinational ATPG

Types of Patterns
BASIC PATTERNS: Tool generates Basic patterns by default for stuck-at

 Initialize scan chain

 Force primary inputs

 Measure primary outputs

 Pulse capture clock

 Unload the scan chains meanwhile load new patterns

MULTILOAD PATTERNS: are capture patterns, for transition. Also known as sequential patterns

RAM SEQUENTIAL PATTERNS: to propagate fault effects through RAM & thoroughly test the circuit
associated with RAM, tool generate a special patterns called Ram Sequential Patterns
Patterns format
 WGL
 ASIC
 VERILOG
 BD
 OCC Controller
To generate shift clock and PLL clock during Transition
Fault model
When TM=1, DFT mode
 SE=1(shift clk), PLL bypass=1(to bypass PLL clk)
o/p=ATE clk is activated to provide shift clock
 SE=0(capture clock),
PLL bypass=0(to activate PLL clk)
o/p=PLL clock
THANK YOU