EFFECTS OF PVT ON DELAY

• The variation sources are Process, Voltage, and Temperature (PVT).

• We must aim to design a circuit that will operate reliably operate over
all extremes of these three variables. Failure to do so causes circuit
problems, poor yield.
Process Variation
• Process variation is the deviation in attributes of transistor during the
fabrication.
• For devices, the most important variations are channel length L and
threshold voltage Vt.
• These variations are caused by
Photolithography proximity effects.
Plasma etch dependencies.
Different doping concentrations and annealing effects.
Oxide thickness variation.
Effect Of Process On Delay

• Consider the drain current equation for NMOS

ID = (1/2)μnCox (W/L)(VGS – VTh)2

• Delay decreases with increase in current.

• From this relation, we say that
delay is more for slow process
MOSFETs and it is less for fast
process MOSFETs
• There are separate model files for
every process corner.
Voltage
• Lets say chip is operating at 1V. So there are chances that at certain
instance of time this voltage may vary.
• It can go to 1.1V or 0.9V. To take care of this scenerio, we consider
voltage variation.
• The important reasons for supply voltage fluctuations are
IR drop is caused by the current flow over the parasitic resistance of the power
grid. IR drop reduces the supply voltage from the required value.
The second important reason for voltage variation is supply noise caused by
parasitic inductance in combination with resistance and capacitance.
The current through parasitic inductance causes the voltage bounce. Both
these effects together can not only lead to voltage drops but also voltage
overshoot.
Supply voltage that any chip works on is given externally. It can come from
DC source or some voltage regulator. Voltage regulator will not give same
voltage over a period of time. It can go above or below the expected voltage.
Effect Of Voltage On Delay
Temparature
• The temperature at the junction inside the chip can vary within a big
range and that’s why temperature variation need to be considered.
• Carrier mobility decreases with temperature.

• The magnitude of the threshold voltage decreases nearly linearly with

temperature and may be approximated by
• Delay of a cell increases with
increase in temperature. But this
is not true for all technology
nodes.
• For deep sub-micron
technologies this behaviour is
contrary. This phenomenon is
called as temperature
inversion.
Why Temperature inversion happens?

Consider the current equation of a MOSFET for better understanding

ID = (1/2)μnCox (W/L)(VGS – VTh)2

• In the higher technology node, where the supply voltage is very high,
the effect of VTh is very low as (VGS – VTh) value is large.
• Hence mobility plays major role in deciding current.
• So at higher technology nodes, when the temperature increases
mobility decreases and as a result the delay will increase.
• At the lower technology node (specifically, less than 65nm), the
supply voltage is very low, so the (VGS – VTh) difference is small and
the square of this value is very small resulting reduced ID current.
• Which increases delay at lower temperature. Where at other end above
65nm delay decreases at lower temperature.
Thank You