Scribd Logo
Upload

Welcome to Scribd!

  • Instructors: Dr. Phillip Jones

    Uploaded by

    skarthikpriya
    26 views44 pages
    The document discusses memory mapped I/O and GPIO ports on microcontrollers. It describes how the TM4C123 microcontroller has 64 pins that can be configured as GPIO ports or have alternate functions. It has 6 GPIO ports labeled A through F, each with 8 pins that can be individually configured as inputs or outputs through memory mapped registers. The document provides examples of C code using memory addresses to directly set the configuration and data registers to control the GPIO pins.

    Original Description:

    Original Title

    GPIO

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document discusses memory mapped I/O and GPIO ports on microcontrollers. It describes how the TM4C123 microcontroller has 64 pins that can be configured as GPIO ports or have alternate functions. It has 6 GPIO ports labeled A through F, each with 8 pins that can be individually configured as inputs or outputs through memory mapped registers. The document provides examples of C code using memory addresses to directly set the configuration and data registers to control the GPIO pins.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pptx, pdf, or txt
    26 views44 pages

    Instructors: Dr. Phillip Jones

    Uploaded by

    skarthikpriya
    The document discusses memory mapped I/O and GPIO ports on microcontrollers. It describes how the TM4C123 microcontroller has 64 pins that can be configured as GPIO ports or have alternate functions. It has 6 GPIO ports labeled A through F, each with 8 pins that can be individually configured as inputs or outputs through memory mapped registers. The document provides examples of C code using memory addresses to directly set the configuration and data registers to control the GPIO pins.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pptx, pdf, or txt
    of 44

    GPIO

    Instructors:
    Dr. Phillip Jones

    http://class.ece.iastate.edu/cpre288 1
    Memory Mapped I/O

    http://class.ece.iastate.edu/cpre288 43
    Microcontroller / System-on-Chip (SoC)
    Microco ntrolle r Outs ide
    P rogram Da ta
    Wo rld
    Me mo ry CPU
    Me mo ry

    De vice s GPIO
    Inte rrupts
    ADC PCTL
    CFG|DATA|STATUS 7
    0 6
    5
    UAR T X 4
    CFG|DATA|STATUS
    NV IC Y AFSEL
    3
    Time rs 0
    1 2
    CFG|DATA|STATUS
    1
    GPIO_ DATA 0

    http://class.ece.iastate.edu/cpre288 44
    Memory Mapped I/O
    •Package Pins
    •Pins with shared (multiplexed) functionality
    – General Purpose I/O
    – Device I/O
    •Memory mapped registers
    – Configuration registers
    – Data registers
    – Status registers

    http://class.ece.iastate.edu/cpre288 45
    TM4C123 I/O Ports
    • 64 package pins

    http://class.ece.iastate.edu/cpre288 46
    TM4C123 I/O Ports
    • 64 package pins
    Allows So ftware to acces s the
    wo rld outs ide of the chip

    http://class.ece.iastate.edu/cpre288 47
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits

    http://class.ece.iastate.edu/cpre288 48
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits

    PORT A

    http://class.ece.iastate.edu/cpre288 49
    TM4C123 I/O Ports
    PORT
    • 64 package pins B
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits

    http://class.ece.iastate.edu/cpre288 50
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits
    PORT
    C

    http://class.ece.iastate.edu/cpre288 51
    TM4C123 I/O Ports
    PORT PORT
    • 64 package pins D D
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits

    PORT D

    http://class.ece.iastate.edu/cpre288 52
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits
    PORT E

    http://class.ece.iastate.edu/cpre288 53
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each 8-bits

    PORT F

    PORT F

    http://class.ece.iastate.edu/cpre288 54
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each
    • Many 8-bitshave
    GPIOs
    alternate functions

    http://class.ece.iastate.edu/cpre288 55
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each
    • Many 8-bitshave
    GPIOs
    alternate functions

    http://class.ece.iastate.edu/cpre288 56
    TM4C123 I/O Ports
    • 64 package pins
    • 6 GPIOs Ports(A –
    F)
    –Each
    • Many 8-bitshave
    GPIOs
    alternate functions

    s elect
    U0T x
    PA1

    http://class.ece.iastate.edu/cpre288 57
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Da ta
    Wo rld
    Me mo ry CPU
    Me mo ry

    De vice s GPIO
    Inte rrupts
    SW write s Configuration Register

    HW writes Da ta Regis ter


    s elect
    U0T x
    PA1

    S oftware write s Da ta Regis ter


    http://class.ece.iastate.edu/cpre288 59
    CPRE 288 Microntroller: Full Memory
    Map

    70
    Memory Mapped General Purpose I/O (GPIO) Ports

    TM4C123GH6PM:
    • 6 general purpose I/O ports: Port A, B, C, D, E,
    F
    • Processor communicates with them through
    memory mapped registers.
    • with
    A seteach port.
    of data and control registers associated

    http://class.ece.ia7s2tate.edu/cpre288 72
    Memory Mapped General Purpose I/O (GPIO) Ports

    • Processor communicates with arbitrary attachments using ports


    • Each GPIO port has several registers, we will focus on 4.

    SYSCTL_RCGCGPIO_R – Enables the port’s system


    clock
    GPIO_PORTx_DATA_R – 8bit data register
    (read/write)
    GPIO_PORTx_DEN_R – Digital enable
    GPIO_PORTx_DIR_R – Data direction register
    register

    http://class.ece.iastate.edu/cpre288 73
    Memory Mapped General Purpose I/O (GPIO) Ports

    SYSCTL_RCGCGPIO_R (GPIO Run Mode Clock Gating


    Control)
    • A GPIO port’s clock must be enabled to use its registers.
    (Your program will crash if you attempt to update an GPIO
    port’s
    • registers
    bits 5-0 inwithout enabling its clock)represent ports
    SYSCTL_RCGCGPIO_R
    F-A.
    E.g.:
    //Enable Port F & B clocks
    SYSCTL_RCGCGPIO_R |= 0b100010;

    http://class.ece.iastate.edu/cpre288 74
    Memory Mapped General Purpose I/O (GPIO) Ports

    GPIO_PORTx_DEN_R (GPIO Digital Enable Register)


    – Writing ‘0’to a bit disables the digital functionality
    for the corresponding pin of the Port.
    – Writing ‘1’to a bit enables the digital functionality
    for the corresponding pin of the Port.

    Example:
    // Enable Digital functionality for pin
    // 8 and 0 of Port A, and preserve the others
    GPIO_PORTA_DIR_R |= 0b10000001;

    http://class.ece.ia7s5tate.edu/cpre288 75
    Memory Mapped General Purpose I/O (GPIO) Ports

    GPIO_PORTx_DIR_R (GPIO Direction Register)


    – Writing ‘0’to a bit programs the corresponding pin
    of the Port as input
    – Writing ‘1’to a bit programs the corresponding pin
    of the Port as output

    Example:
    //All bits of port A prog for input except bit0
    GPIO_PORTA_DIR_R = 0b00000001;

    http://class.ece.ia7s6tate.edu/cpre288 76
    Memory Mapped General Purpose I/O (GPIO) Ports
    GPIO_PORTX_DATA_R
    Register:
    For output configured port: If a bit in in the Port’s DATA register
    is written when the corresponding pin is configured as an
    output, then the port’s pin will be driven with this value.

    Write to a port using its DATA register.


    E.g.:
    SYSCTL_RCGCGPIO_R |= 0b000001; //enable PORTA clock
    GPIO_PORTA_DIR_R = 0xFF; //set port A dir to output
    GPIO_PORTA_DEN_R = 0xFF; //Enable pins 0-7
    GPIO_PORTA_DATA_R = my_char;//set port A to my_char
    Give C code witho ut us ing the
    “magic” v arible name.

    http://class.ece.iastate.edu/cpre288 77
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Addres s Decode
    Da ta
    Wo rld
    CPU 0x20000000
    Me mo ry 0x20007FFF Me mo ry

    0x40000000 De vice s GPIO


    Inte rrupts 0x400FFFFF

    GPIO_PORTA_DATA_R = my_char;
    0x4000C000 - 0x4000CFFF
    UAR T s elect
    CFG|DATA|STATUS

    Give C code witho ut us ing the


    “magic” variable name. PA1
    char *ptr; 76 5 4 3 21 0
    ptr = 0x4000_43FC;
    *ptr = my_char; 0x400043FCGPIO_ PORTA_ DATA
    http://class.ece.iastate.edu/cpre288 78
    Memory Mapped General Purpose I/O (GPIO) Ports
    GPIO_PORTX_DATA_R
    Register:
    For output configured port: If a bit in in the Port’s DATA register
    is written when the corresponding pin is configured as an
    output, then the port’s pin will be driven with this value.

    Write to a port using its DATA register.


    E.g.:
    SYSCTL_RCGCGPIO_R |= 0b000001; //enable PORTA clock
    GPIO_PORTA_DIR_R = 0xFF; //set port A dir to output
    GPIO_PORTA_DEN_R = 0xFF; //Enable pins 0-7
    GPIO_PORTA_DATA_R = my_char;//set port A to my_char

    Directly using the definition of GPIO_PORTA_DATA_R


    *((char *)0x400043FC) = my_char;
    http://class.ece.iastate.edu/cpre288 79
    Memory Mapped General Purpose I/O (GPIO) Ports
    // tm4c123gh6pm.h
    //*****************************************************************************
    // GPIO registers (PORTA)
    //*****************************************************************************
    #define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
    #define (*((volatile unsigned long
    GPIO_PORTA_DATA_R *)0x400043FC))
    #define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
    #define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
    #define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
    #define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
    #define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
    #define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
    #define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
    #define GPIO_PORTA_AFSEL_R (*((volatile
    GPIO_PORTA_ICR_R (*((volatile unsigned
    unsigned long
    long *)0x4000441C))
    #define
    *)0x40004420)) (*((volatile unsigned long *)0x40004500))
    GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004504))
    #define (*((volatile unsigned long *)0x40004508))
    GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x4000450C))
    #define (*((volatile unsigned long *)0x40004510))
    GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004514))
    #define (*((volatile unsigned long *)0x40004518))
    GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000451C))
    #define (*((volatile unsigned long *)0x40004520))
    GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004524))
    #define GPIO_PORTA_AMSEL_R (*((volatile unsigned long
    *)0x40004528))
    GPIO_PORTA_PDR_R
    #define GPIO_PORTA_ADCCTL_R
    GPIO_PORTA_PCTL_R (*((volatile
    (*((volatile unsigned
    unsigned long
    long
    *)0x40004530))
    *)0x4000452C))
    GPIO_PORTA_SLR_R
    #define GPIO_PORTA_DMACTL_R (*((volatile unsigned long 80
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Addres s Decode
    Da ta
    Wo rld
    CPU 0x20000000
    Me mo ry 0x20007FFF Me mo ry

    0x40000000 De vice s GPIO


    Inte rrupts 0x400FFFFF

    0x4000C000 - 0x4000CFFF
    UAR T s elect
    CFG|DATA|STATUS

    PA1
    76 5 4 3 21 0

    0x400043FCGPIO_ PORTA_ DATA


    http://class.ece.iastate.edu/cpre288 84
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Addres s Decode
    Da ta
    Wo rld
    CPU 0x20000000
    Me mo ry 0x20007FFF Me mo ry

    0x40000000 De vice s GPIO


    Inte rrupts 0x400FFFFF

    0x4000C000 - 0x4000CFFF
    UAR T s elect
    CFG|DATA|STATUS

    Time rs PA1
    CFG|DATA|STATUS
    76 5 4 3 21 0

    0x400043FCGPIO_ PORTA_ DATA


    http://class.ece.iastate.edu/cpre288 85
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Addres s Decode
    Da ta
    Wo rld
    CPU 0x20000000
    Me mo ry 0x20007FFF Me mo ry

    0x40000000 De vice s GPIO


    Inte rrupts 0x400FFFFF
    ADC
    CFG|DATA|STATUS

    UAR T s elect
    CFG|DATA|STATUS
    ?
    Time rs PA1
    CFG|DATA|STATUS
    76 5 4 3 21 0

    0x400043FCGPIO_ PORTA_ DATA


    http://class.ece.iastate.edu/cpre288 86
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Addres s Decode
    Da ta
    Wo rld
    CPU 0x20000000
    Me mo ry 0x20007FFF Me mo ry

    0x40000000 De vice s GPIO


    Inte rrupts 0x400FFFFF
    ADC
    CFG|DATA|STATUS

    UAR T s elect
    CFG|DATA|STATUS s elect

    Time rs PA1
    CFG|DATA|STATUS
    76 5 4 3 21 0

    0x400043FCGPIO_ PORTA_ DATA


    http://class.ece.iastate.edu/cpre288 87
    TM4C123 I/O Ports
    Microco ntrolle r Outs ide
    P rogram Addres s Decode
    Da ta
    Wo rld
    CPU 0x20000000
    Me mo ry 0x20007FFF Me mo ry

    0x40000000 De vice s GPIO


    Inte rrupts 0x400FFFFF
    ADC
    CFG|DATA|STATUS

    UAR T s elect
    CFG|DATA|STATUS s elect

    Time rs PA1
    CFG|DATA|STATUS
    76 5 4 3 21 0

    0x400043FCGPIO_ PORTA_ DATA


    http://class.ece.iastate.edu/cpre288 88
    Microcontroller / System-on-Chip (SoC)
    Microco ntrolle r Outs ide
    P rogram Da ta
    Wo rld
    Me mo ry CPU
    Me mo ry

    De vice s GPIO
    Inte rrupts
    ADC PCTL
    CFG|DATA|STATUS 7
    0 6
    5
    UAR T X 4
    CFG|DATA|STATUS
    NV IC Y AFSEL
    3
    Time rs 0
    1 2
    CFG|DATA|STATUS
    1
    GPIO_ DATA 0

    http://class.ece.iastate.edu/cpre288 89
    Microcontroller / System-on-Chip (SoC)
    Microco ntrolle r Outs ide
    P rogram Da ta
    Wo rld
    Me mo ry CPU
    Me mo ry

    De vice s GPIO
    Inte rrupts
    ADC PCTL
    CFG|DATA|STATUS 7
    0 6
    5
    UAR T X 4
    CFG|DATA|STATUS
    NV IC Y AFSEL
    3
    Time rs 0
    1 2
    CFG|DATA|STATUS
    1
    GPIO_ DATA 0

    http://class.ece.iastate.edu/cpre288 90
    GPIO Port: Alternative Function Architecture

    Ha rdwa re write s
    (Alte rna tive Function)

    S oftware write s
    (GP IO)

    Figure 2.17 Function block diagram of Analog/Digital GPIO control.


    http://class.ece.iastate.edu/cpre288 91
    Microcontroller / System-on-Chip (SoC)
    Microco ntrolle r Outs ide
    P rogram Da ta
    Wo rld
    Me mo ry CPU
    Me mo ry

    De vice s GPIO
    Inte rrupts
    ADC PCTL
    CFG|DATA|STATUS 7
    0 6
    5
    UAR T X 4
    CFG|DATA|STATUS
    NV IC Y AFSEL
    3
    Time rs 0
    1 2
    CFG|DATA|STATUS
    1
    GPIO_ DATA 0

    http://class.ece.iastate.edu/cpre288 92
    GPIO Port: Alternative Function Architecture

    • GPIOAFSEL: For each wire select GPIO or Alternative


    Function
    • GPIOPCTL: For each wire choose which Alternative Function
    31 7 6 5 4 3 2 1 0

    GPIOAFSEL …... 1 1

    31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
    GPIOPCTL PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0

    Table 2.6 Table 2.6


    PMC6 Bit Encoding PMC0 Bit Encoding
    (1, 2, 3, … 9, 14) (1, 2, 3, … 9, 14)
    0001, 0010, 0011, 0001, 0010, 0011,
    … 1001, 1110 … 1001, 1110

    Figure 2.19 The illustration for GPIOAFSEL and GPIOPCTL registers.

    http://class.ece.iastate.edu/cpre288 93
    GPIO Port: Alternative Function Architecture
    Table 2.6 GPIO Pins and Alternate Functions
    Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
    I/O Pin
    Function 1 2 3 4 5 6 7 8 9 14
    PA0 17 - U0RX - - - - - - CAN1RX - -
    PA1 18 - U0TX - - - - - - CAN1TX - -
    PA2 19 - - SSI0CLK - - - - - - - -
    PA3 20 - - SSI0FSS - - - - - - - -
    PA4 21 - - SSI0RX - - - - - - - -
    PA5 22 - - SSI0TX - - - - - - - -
    PA6 23 - - - I2C1SCL - M1PWM2 - - - - -
    PA7 24 - - - I2C1SDC - M1PWM3 - - - - -
    PB0 45 USB0ID U1RX - - - - - T2CCP0 - - -
    PB1 46 USB0VBUS U1TX - - - - - T2CCP1 - - -
    PB2 47 - - - I2C0SCL - - - T3CCP0 - - -
    PB3 48 - - - I2C0SDC - - - T3CCP1 - - -
    PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX - -
    PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX - -
    PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 - - -
    PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 - - -
    TCK
    PC0 52 - - - - - - T4CCP0 - - -
    SWCLK
    TMS
    PC1 51 - - - - - - T4CCP1 - - -
    SWDIO
    PC2 50 - TDI - - - - - T5CCP0 - - -
    PC3 49 - TDO - - - - - T5CCP1 - - -
    SWO
    PC4 16 C1- U4RX U1RX - M0PWM6 - IDX1 WT0CCP0 U1RTS - -
    PC5 15 C1+ U4TX U1TX - M0PWM7 - PHA1 WT0CCP1 U1CTS - -
    http://class.ece.iastate.edu/cpre288 94
    GPIO Port: Alternative Function Architecture
    • What values do GPIOAFSEL and GPIOPCTL need to be
    to configure Port B to use UART1
    given
    TX?

    http://class.ece.iastate.edu/cpre288 95
    GPIO Port: Alternative Function Architecture
    • What values do GPIOAFSEL and GPIOPCTL need to be
    configure
    given to Port B to use UART1 s
    TX? Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
    I/O Pin
    Function 1 2 3 4 5 6 7 8
    PB0 45 USB0ID U1RX - - - - - T2CCP0 -
    PB1 46 USB0VBUS U1TX - - - - - T2CCP1 -
    PB2 47 - - - I2C0SCL - - - T3CCP0 -
    PB3 48 - - - I2C0SDC - - - T3CCP1 -
    PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX
    PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX
    PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 -
    PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 -

    http://class.ece.iastate.edu/cpre288 96
    GPIO Port: Alternative Function Architecture
    • What values do GPIOAFSEL and GPIOPCTL need to be
    configure
    given to Port B to use UART1 s
    TX? Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
    I/O Pin
    Function 1 2 3 4 5 6 7 8
    PB0 45 USB0ID U1RX - - - - - T2CCP0 -
    PB1 46 USB0VBUS U1TX - - - - - T2CCP1 -
    PB2 47 - - - I2C0SCL - - - T3CCP0 -
    PB3 48 - - - I2C0SDC - - - T3CCP1 -
    PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX
    PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX
    PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 -
    PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 -

    GPIO_ PORTB_AFSEL
    7 6 5 4 3 2 1 0

    http://class.ece.iastate.edu/cpre288 97
    GPIO Port: Alternative Function Architecture
    • What values do GPIOAFSEL and GPIOPCTL need to be
    configure
    given to Port B to use UART1 s
    TX? Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
    I/O Pin
    Function 1 2 3 4 5 6 7 8
    PB0 45 USB0ID U1RX - - - - - T2CCP0 -
    PB1 46 USB0VBUS U1TX - - - - - T2CCP1 -
    PB2 47 - - - I2C0SCL - - - T3CCP0 -
    PB3 48 - - - I2C0SDC - - - T3CCP1 -
    PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX
    PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX
    PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 -
    PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 -

    GPIO_ PORTB_AFSEL
    7 6 5 4 3 2 1 0

    P ortB
    W ire 1
    http://class.ece.iastate.edu/cpre288 98
    GPIO Port: Alternative Function Architecture
    • What values do GPIOAFSEL and GPIOPCTL need to be
    configure
    given to Port B to use UART1 s
    TX? Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
    I/O Pin
    Function 1 2 3 4 5 6 7 8
    PB0 45 USB0ID U1RX - - - - - T2CCP0 -
    PB1 46 USB0VBUS U1TX - - - - - T2CCP1 -
    PB2 47 - - - I2C0SCL - - - T3CCP0 -
    PB3 48 - - - I2C0SDC - - - T3CCP1 -
    PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX
    PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX
    PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 -
    PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 -

    GPIO_ PORTB_PCTL
    PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_ PORTB_AFSEL
    7 6 5 4 3 2 1 0

    31 28 27 24 23 21 20 16 15 12 11 87 43 0

    P ortB
    W ire 1
    http://class.ece.iastate.edu/cpre288 99
    GPIO Port: Alternative Function Architecture
    • What values do GPIOAFSEL and GPIOPCTL need to be
    configure
    given to Port B to use UART1 s
    TX? Analog Digital Functions (GPIOPCTL PMCx Bit Field Encoding)
    I/O Pin
    Function 1 2 3 4 5 6 7 8
    PB0 45 USB0ID U1RX - - - - - T2CCP0 -
    PB1 46 USB0VBUS U1TX - - - - - T2CCP1 -
    PB2 47 - - - I2C0SCL - - - T3CCP0 -
    PB3 48 - - - I2C0SDC - - - T3CCP1 -
    PB4 58 AIN10 - SSI2CLK - M0PWM2 - - T1CCP0 CAN0RX
    PB5 57 AIN11 - SSI2FSS - M0PWM3 - - T1CCP1 CAN0TX
    PB6 1 - - SSI2RX - M0PWM0 - - T0CCP0 -
    PB7 4 - - SSI2TX - M0PWM1 - - T0CCP1 -

    GPIO_ PORTB_PCTL
    PMC7 PMC6 PMC5 PMC4 PMC3 PMC2 PMC1 PMC0 GPIO_ PORTB_AFSEL
    7 6 5 4 3 2 1 0

    31 28 27 24 23 21 20 16 15 12 11 87 43 0

    P ortB
    W ire 1
    http://class.ece.iastate.edu/cpre288 100

    You might also like