Control Unit

BITS Pilani S Mohan

Pilani Campus
Introduction

• An instruction execution involves the execution of

a sequence of sub steps, called cycles
– Ex: Fetch cycle, Indirect cycle, execute cycle, interrupt cycle

• Each cycle in turn is made up of a sequence of

more fundamental operations called micro-
operations
– Ex: Register to Register transfer, Register to external bus transfer, ALU
operation etc.

BITS Pilani, Pilani Campus

What Control Unit does?
• Generates the control signals to execute each
micro-operation

• Causes the processor to execute micro-

operations in proper sequence

• The control signals generated by the CU cause

the opening and closing of logic gates, resulting in
the execution of the micro-ops

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Constituent Elements of Program Execution

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Fetch - 4 Registers

• Memory Address Register (MAR)

– Connected to address bus
– Specifies address for read or write operand
• Memory Buffer Register (MBR)
– Connected to data bus
– Holds data to write or last data read
• Program Counter (PC)
– Holds address of next instruction to be fetched
• Instruction Register (IR)
– Holds last instruction fetched

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Data Flow (Fetch Diagram)

• Address of next instruction is in PC

• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on
data bus
• Data from data bus copied into MBR
• PC incremented by 1 (in parallel with
data fetch from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches

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Fetch Sequence (symbolic)

t1: MAR <- (PC)

t2: MBR <- (memory)
PC <- (PC) + I
t3: IR <- (MBR)
(tx = time unit/clock cycle)

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Rules for Clock Cycle Grouping

• Proper sequence must be followed

– MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
– Must not read & write same register at same time
– MBR <- (memory) & IR <- (MBR) must not be in
same cycle
• Also: PC <- (PC) +I involves addition
– Use ALU
– May need additional micro-operations

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Indirect Cycle

• MAR <- (IRaddress) - address field of IR

• MBR <- (memory)
• IRaddress <- (MBRaddress)
• MBR contains an address
• IR is now in same state as if direct addressing had been used

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Interrupt Cycle

• t1:MBR <-(PC)
• t2:MAR <- save-address (Where to save the
PC?)
• PC <- routine-address
• t3:memory <- (MBR)

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 Execute Cycle (ADD)

• Different for each instruction

• e.g. ADD R1, X
– Add the contents of location X to Register R1, result in R1
• t1:MAR <- (IRaddress)
• t2:MBR <- (memory)
• t3:R1 <- R1 + (MBR)
• Overlap of micro-operations is not possible here!!!

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Execute Cycle (ISZ)

• ISZ X - increment and skip if zero

– The content of memory location X is incremented
by 1. If the result is 0, the next instruction is
skipped.
– t1: MAR <- (IRaddress)
– t2: MBR <- (memory)
– t3: MBR <- (MBR) + 1
– t4: memory <- (MBR)
– if (MBR) == 0 then PC <- (PC) + I

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Execute Cycle (BSA)

• BSA X - Branch and save address

– Address of instruction following BSA is saved in
memory location X and execution continues from
X+I
– t1: MAR <- (IRaddress)
– MBR <- (PC)
– t2: PC <- (IRaddress)
– memory <- (MBR)
– t3: PC <- (PC) + I

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Instruction Cycle

• Each phase decomposed into sequence of elementary

micro-operations
– E.g. fetch, indirect, and interrupt cycles
• Execute cycle
– One sequence of micro-operations for each opcode
• Need to tie sequences together

• Assume new 2-bit register

– Instruction cycle code (ICC) designates which part of cycle is
processor in
• 00: Fetch, 01: Indirect, 10: Execute, 11: Interrupt

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Flowchart for Instruction Cycle

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Basic Elements of the processor

• ALU
• Registers
• Internal data paths
• External data paths
• Control Unit

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Types of Micro-operation

• Transfer data between registers

• Transfer data from register to external
interface
• Transfer data from external interface to
register
• Perform arithmetic or logical ops

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 Control Unit –Inputs

• Clock
– To keep time
• Instruction register
– Op-code for current instruction
determines which micro-
instructions are performed
• Flags
– State of CPU
– Results of previous operations
• From control bus
– Interrupts, Acknowledgements
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Control Unit – Outputs

• Control Signals: Within CPU

– Cause data movement
– Activate specific ALU functions

• Control Signals: Via control bus

– To memory & I/O modules

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Data Paths and Control Signals

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Micro Operations And Control
Signals

• Fetch Control Signals

– t1: MAR <- (PC) C2

– t2: MBR <- (memory)

C5 , C R
PC <- (PC) +I
– t3: IR <- (MBR) C4

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