SOURCES OF POWER DISSIPATION

By
Dr. M. Madhusudhan Reddy
M.Tech., Ph.D
• The power dissipation in conventional CMOS
digital circuits can be classified into three
main components.

1. The dynamic (switching) power dissipation

2. The short-circuit power dissipation and

3. The Static (leakage) power dissipation.

 Dynamic power dissipation
• It is caused by the charging and discharging of the
output Load capacitance.
• It is the dominant source of power dissipation
(75%).

• It is represented by
Pdynamic = αCLVDD2fclk.

Fig. Switching Power Dissipation

 Short-circuit power dissipation

 When both pull-up and pull-

down networks are conducting
for a small duration and there is
a direct path b/w VDD to
GND. 
 when both transistor are ON
momentarily the short circuit
comes in the form of spike
(10%).
 It is represented by Pshort-circuit =
Is/c VDD

(W/L)pMOS ≈2.5 (W/L)nMOS

 Static power dissipation

• The static or leakage power dissipation is always present due to the

leakage current of the transistors even if the circuit is not switching
(15%).
• It is given by Pstatic = Ileakage VDD
• It is becoming comparable to dynamic power with the continuous
scaling down of CMOS technology (< 90 nm)
• Reduce static power – Selectively use ratioed circuits.
– Selectively use low Vth devices.
• Leakage reduction: Stacked devices, body bias,
low temperature.
• The total power dissipation of a CMOS circuit is the
sum of 3 power dissipations and expressed as
Ptotal = Pdynamic + Ps/c + Pstatic.
Pseudo-nMOS Inverter
 Need for low-power VLSI
• To increase battery life time

• Increase of handheld devices

• To enhance noise margin

• To reduce energy costs

• To reduce use of natural resources

• To increase system reliability

• To reduce power supply noise
• For better performance
THANK YOU