Analog to Digital Conversion

(ADC)
COE 306: Introduction to Embedded Systems
Dr. Aiman El-Maleh
Computer Engineering Department

College of Computer Sciences and Engineering

King Fahd University of Petroleum and Minerals
 Next . . .
 A/D Conversion Process
 ADC Process Accuracy
 Conversion Time & Converter Rate
 Types of ADC Techniques

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Signal Types
Analog Signals
 An analog signal is a continuous signal that contains
time-varying quantities. Measures one quantity in terms
of some other quantity.
 Example
 in an analog audio signal, the instantaneous voltage of the signal
varies continuously with the pressure of the sound

t
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Signal Types
Digital Signals
 A digital signal is a signal that is being used to
represent data as a sequence of discrete values; at any
given time it can only take on one of a finite number of
values
 The precision of the signal is determined by how many
samples are recorded per unit of time

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Analog-Digital Converter (ADC)
 An electronic integrated circuit which converts a signal
from analog (continuous) to digital (discrete) form
 Provides a link between the analog world of transducers
and the digital world of signal processing and data
handling

t t

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 A/D Conversion Process
Two main steps:
1. Sampling and Holding
2. Quantization and Encoding

Analog-to-Digital Converter

Quantizing
and
Encoding

Sampling and
Hold
t
Input: Analog Signal t

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 A/D Conversion Process
Sampling & Hold
 Measuring analog signals
at uniform time intervals
 Ideally twice as fast as what
we are sampling t

 Digital system works with

discrete states
 Taking samples from each
location
 Reflects sampled and hold
signal
 Digital approximation

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 A/D Conversion Process
Quantizing Encoding
 Separating the input  Assigning a unique digital
signal into K discrete code to each state
states
State Value Code
 K=2N
0 0V 00
 N is the number of bits of
1 1.25 V 01
the ADC
2 2.5 V 10
 Analog quantization size 3 3.75 V 11
 Q=(Vmax-Vmin)/2N
 Q is the Resolution

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 A/D Conversion Process
 Quantization & Coding
 Use original analog signal
 Apply 2 bit coding
 Apply 3 bit coding
 Better representation of
input information with
additional bits

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 ADC Process-Accuracy
Sampling Rate, Ts Resolution (bit depth), Q
 Based on number of  Improves accuracy in
steps required in the measuring amplitude of
conversion process analog signal
 Increases the maximum
frequency that can be
measured

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 ADC Process-Accuracy
 Increasing sampling rate and the number of used
quantized values result in better accuracy ADC signals.

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 ADC-Error Possibilities
 Aliasing (sampling)
 An effect caused when sampled signals become
indistinguishable from each other (aliases of one another)
 Occurs when the input signal is changing much faster than the
sample rate
 Should follow the Nyquist Rule when sampling
 Use a sampling frequency at least twice as high as the maximum
frequency in the signal to avoid aliasing
 fsample > 2 x fsignal

 Quantization Error (resolution)

 Optimize resolution
 Dependent on ADC converter of microcontoller

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Aliasing Example

• Two different sinusoids fit same set of samples

• Aliasing of two sine waves (f=0.9 and f=0.1).

• Sampling period T=1.0.

Source: https://en.wikipedia.org/wiki/Aliasing
Processes and Operating Systems
COE 306– Introduction to Embedded System– KFUPM
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 Quantization Error & Effective
Number of Bits
 Encoding a signal (A/2) sinwt with A being the full2 scale2
using n-bit ADC will give an error variance  2  q  A 2 n
12 12 2
 A2 
 
 x2 
 Signal to Noise Ratio SNR 10 log 2  10 log  82   6 n  1.8 dB
  A 
 Effective number of bits of an n-bit ADC  12 2 2 n 

 n’ giving the correct SNR
 Example:
 AD9235 12-bit 20 to 65 MHz
3.5
q q
3
 
2.5 2 2
 SNR = 70 dB 2

1.5

 Effective number of bits = 11.4 1 q 1

q


2 2 2
  q x dx
0.5
e(x) q 
0 2
0 0.5 1 1.5 2 2.5 3 3.5

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Conversion Time & Converter Rate
 Conversion Time
 Required time (tc) before the converter can provide valid output
data
 Converter Throughput Rate
 The number of times the input signal can be sampled
maintaining full accuracy
 Inverse of the total time required for one successful conversion
 Input voltage change during the conversion process
introduces an undesirable uncertainty
 Full conversion accuracy is realized only if this
uncertainty is kept low below the converter’s resolution

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Conversion Time & Converter Rate
 Rate of Change x tc  resolution dV FS
( ) max  n
 Example dt 2 tc
 8-bit ADC
 Conversion Time: 100sec
 Sinusoidal input v  A sin(2 ft )
i
 Rate of change
dvi
 2 fA cos(2 ft )  2 fA
dt
 Let FS = 2A
2A Limited to Low frequency of 12.4 Hz
2 fA 
2 n tc Few Applications
1
f  n
 12.4 Hz
2  tc
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Types of ADC Techniques
 Counter or Tracking ADC
 Flash ADC
 Successive Approximation ADC
 Single Slope Integration ADC
 Dual Slope ADC
 Delta-Sigma ADC

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Counter Type ADC
 Operation
 Reset and Start Counter
 DAC convert Digital output of
Counter to Analog signal
 Compare Analog input and Output
of DAC
 Vin > VDAC
– Continue counting
 Vin ≤ VDAC
– Stop counting
 Digital Output = Output of Counter
 Disadvantage
 Conversion time (tc) not constant
 Tc(max)=(2n -1) Tclk

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Tracking Type ADC
 Tracking or Servo Type
 Using Up/Down Counter to track input signal continuously
 For slow varying input
 Disadvantage
 tc not constant
 Tc(max)=(2n -1) Tclk

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash ADC
 Also known as parallel ADC
 Elements
• Priority Encoder – Converts
output of comparators to binary
• Comparators

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash ADC
 Algorithm
 Vin value lies between two
comparators
 Resolution ;
 N= Encoder Output bits
 Comparators => 2N-1

 Example: Vref 8V, Encoder 3-bit

 Resolution = 1.0V
 Comparators 23-1=7
 1 additional encoder bit ->
2 x # Comparators

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash ADC
 Example
 Vin = 5.5V, Vref= 8V
 Vin lies in between Vcomp5 & Vcomp6
 Vcomp5 = Vref*5/8 = 5V
 Vcomp6 = Vref*6/8 = 6V
 Comparator 1 - 5 => output 1
 Comparator 6 - 7 => output 0
 Encoder Octal Input = sum(0011111) = 5
 Encoder Binary Output = 1 0 1

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash ADC
 Typical performance:
 4 to 12 bits
 15 to 300 MHz
 High power
 Half-Flash ADC
 2-step technique
 1st flash conversion with 1/2 the precision
 Subtracted with a DAC
 New flash conversion

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Half-Flash ADC
 Example
 4-bit precision is divided into two stages with each stage
generating 2 bits
 In the first stage, the comparators will be fed by the values
12/16Vref, 8/16Vref and 4/16Vref => this will generate 2 bits
 The generated 2 bits will be converted to analog signal using
DAC and then subtracted from the analog signal
 In the second stage, the comparators will be fed by the values
3/16Vref, 2/16Vref and 1/16Vref

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash and Half-Flash ADC
 Given an analog signal in the range of 0v to +5v, it is
required to convert the analog signal value 4.6v into a
digital signal with 4-bit resolution.
 Show the 4-bit converted signal using Flash ADC
 The Flash ADC will have 15 comparators with the first
comparator having a reference value of 15/16*5=4.6875, the
second comparator having the reference value of
14/16*5=4.375, and the 15th comparator having the reference
value of 1/16*5=0.3125. The input will be compared with all
comparators and will be fed to a priority encoder. Since the input
value 4.6 is greater than the reference values of the second
comparator, the priority encoder will generate the value 1110.

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash and Half-Flash ADC
 Show the 4-bit converted signal using Half-Flash ADC
with each Flash ADC generating two bits.
 The first Flash ADC will have 3 comparators with reference
values 12/16*5=3.75, 8/16*5=2.5, and 4/16*5=1.25. Since the
input value 4.6 is greater than the first comparator reference
value, the Flash ADC will generate the code 11. Then using a
DAC, this value will be subtracted from the analog signal value
and will result in the signal 4.6-3.75=0.85. The 2nd Flash ADC
will have 3 comparators with reference values 3/16*5=0.9375,
2/16*5=0.625 and 1/16*5=0.3125. The value 0.85 will be
compared with the 3 reference values and since it is greater
than the 2nd ref. values, the code 10 will be generated. The two
codes will be concatenated and the 4-bit value will be 1110.

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Flash ADC
Advantages Disadvantages
 Simplest in terms of  Lower precision
operational theory  Expensive
 For each additional
 Most efficient in terms output bit, the number
of speed, very fast of comparators is
 limited only in terms of nearly doubled
comparator and gate  i.e. for 8 bits, 255
propagation delays comparators needed

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC
 Most Commonly used in medium to high speed
Converters
 Based on approximating the input signal with binary
code and then successively revising this approximation
until best approximation is achieved
 SAR(Successive Approximation Register) holds the
current binary value

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC
 Uses an n-bit DAC and original analog results
 Performs a binary comparison of VDAC and Vin
 MSB is initialized at 1 for DAC
 If Vin > VDAC (VREF / 2^1) then MSB is set to 1 otherwise 0
 If Vin > VDAC (VREF / 2^(n-i)) for bit i, bit i is set to 1
otherwise 0
 Algorithm is repeated up to LSB
 At end DACin = ADCout
 N-bit conversion requires N comparison cycles
 Conversion Time = N Tclk (independent of input voltage)
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC
 Example DAC bit/voltage
 5-bit ADC, Vin=0.6V, Vref=1V Bit 4 3 2 1 0
Voltage .5 .25 .125 .0625 .03125

 Cycle 1 => MSB=1

SAR = 1 0 0 0 0
VDAC = Vref/2^1 = .5 Vin > VDAC SAR unchanged = 1 0 0 0 0

 Cycle 2
SAR = 1 1 0 0 0
VDAC = .5 +.25 = .75 Vin < VDAC SAR bit3 reset to 0 = 1 0 0 0 0

 Cycle 3
SAR = 1 0 1 0 0
VDAC = .5 + .125 = .625 Vin < VDAC SAR bit2 reset to 0 = 1 0 0 0 0

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC

 Cycle 4
SAR = 1 0 0 1 0
VDAC = .5+.0625=.5625 Vin > VDAC SAR unchanged = 1 0 0 1 0

 Cycle 5
SAR = 1 0 0 1 1
VDAC = .5+.0625+.03125= .59375
Vin > VDAC SAR unchanged = 1 0 0 1 1

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC
 Given an analog signal in the range of 0v to +5v, it is
required to convert the analog signal value 4.6v into a
digital signal with 4-bit resolution.
 Show the 4-bit converted signal using Successive
Approximation ADC
 The 4-bits in the SAR register will have the following weights: 5/2=2.5, 5/4=1.25,
5/8=0.625, 5/16=0.3125. The SAR will be set to the value 1000 and this value
will be converted to the analog value 2.5 and will be compared with the input.
Since the input value 4.6 is greater than 2.5, this bit will remain set. Then the
next bit in the SAR will be set and SAR=1100. This will be converted to the
analog value 2.5+1.25=3.75. Since the input value 4.6 is greater than 3.75, this
bit will remain set. Then the next bit in the SAR will be set and SAR=1110. This
will be converted to the analog value 2.5+1.25+0.625=4.375. Since the input
value 4.6 is greater than 4.375, this bit will remain set. Finally, the last bit in the
SAR will be set and SAR=1111. This will be converted to the analog value
2.5+1.25+0.625+0.3125=4.6875. Since the input value is less than this value,
the last bit in SAR will reset. Thus, the converted value is 1110.
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC
 Example: -5 V to +5 V analog range, n=8

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Successive Approximation ADC
Advantages Disadvantages

 Capable of high speed and  Higher precision successive

reliable approximation ADC’s will be
 Typical conversion time
slower
 1 to 50 ms  Typical number of bits
 Medium accuracy  8 to 16 bits
compared to other ADC
types  Speed limited to ~5Msps
 Good tradeoff between
speed and cost
 Capable of outputting the
binary number in serial (one
bit at a time) format.

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Single Slope Integration ADC
 Start to charge a capacitor at
constant current
 Count clock ticks during this time
 Stop when the capacitor voltage
reaches the input
 Cannot reach high precision
 Capacitor, resistor

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Dual Slope ADC
 Input voltage is applied to input
of integrator and allowed to
ramp for a fixed time period (T1)
 Then, a known reference
voltage of opposite polarity is
applied to integrator and is
allowed to ramp until integrator
output returns to zero (T2)
 The input voltage is computed
as a function of the reference
voltage, the constant run-up
time period, and the measured
run-down time period
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Dual Slope ADC
 Conversion Time
 Worst Case: 2N+1 Tclk
 Example
 12-bit dual slope ADC, Clock frequency=10MHZ, Tc=0.8 ms
 16-bit dual slope ADC, Clock frequency=10MHZ, Tc=13 ms
 Advantages
 Capacitor value is not important although has to be of good
quality
 Typical precision
 12 to 16 bit

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Dual Slope ADC
Advantages Disadvantages
 Insensitive to errors in  Slow
component values  High precision external
 Greater noise immunity components required to
than other ADC types achieve accuracy
 High accuracy

 Due to high accuracy, it is used in digital millimeter

 Not suitable for signal processing applications as it is slow

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Delta-Sigma ADC
 Over sampled input signal
goes to the integrator
 Output of integration is
compared to GND
 1 if ≥ 0 otherwise 0
 Output is serial bit stream
with # of 1’s proportional to
Vin
 1 bit DAC generates +v if
bit is 1 and –v if bit is 0
 Iteration drives integration
of error to zero
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Delta-Sigma ADC

 3 dB reduction in quantization noise for every x2 sampling

 1-bit improvement in in ENOB for every x4 oversampling
Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Delta-Sigma ADC – Noise Shaping
1st order Delta-Sigma

2nd order Delta-Sigma

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Delta-Sigma ADC

 2X increase in sampling rate

 (6L+3) dB increase in SNR (L is the order)
 (L+0.5)-bit increase in ENOB

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Digital Filter (FIR)& Decimator

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Outputs of Delta Sigma Modulator
Input   Out DAC Input   Out DAC
0.4v 0.4v 0.4v 1 +1v 0.8v 0.8v 0.8v 1 +1v
0.4v -0.6v -0.2v 0 -1v 0.8v -0.2v 0.6v 1 +1v
0.4v 1.4v 1.2v 1 +1v 0.8v -0.2v 0.4v 1 +1v
0.4v -0.6v 0.6v 1 +1v 0.8v -0.2v 0.2v 1 +1v
0.4v -0.6v 0.0v 1 +1v 0.8v -0.2v 0.0v 1 +1v
0.4v -0.6v -0.6v 0 -1v 0.8v -0.2v -0.2v 0 -1v
0.4v 1.4v 0.8v 1 +1v 0.8v 1.8v 1.6v 1 +1v
0.4v -0.6v 0.2v 1 +1v 0.8v -0.2v 1.4v 1 +1v
0.4v -0.6v -0.4v 0 -1v 0.8v -0.2v 1.2 1 +1v
0.4v 1.4v 1.0v 1 +1v 0.8v -0.2v 1.0 1 +1v
Average=0.4v Average=0.8v
http://www.analog.com/en/design-center/interactive-design-tools/sigma-delta-adc-tutorial.html

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Outputs of Delta Sigma Modulator

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 Delta-Sigma ADC

Advantages Disadvantages

 High precision  Slow due to

 Low cost oversampling
 External sample & hold
circuits are not required
 Requirements for analog
anti-aliasing filters are
minimum

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 ADC Types Comparison

Processes and Operating Systems COE 306– Introduction to Embedded System– KFUPM
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 ADC Types Comparison

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