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Microprocessors - Meppayil Narayanan
Microprocessors - Meppayil Narayanan
MICROPROCESSORS
Meppayil Narayanan
Sir Syed College
Taliparamba
Kannur
E-mail : meppayilnarayanan@gmail.com
“A Microprocessor is a multipurpose,
programmable, clock driven, register
based electronic device that reads binary
instructions from a storage device called
memory, accepts binary data as input and
processes data according to those
instructions, and provides results as
output.”
EVOLUTIONS OF MICROPROCESSORS
Microprocessor is a semiconductor device
consisting of electronic logic circuits. It is a
programmable device. A set of instructions
written for the microprocessor to perform a task
is called a program.
Microprocessor used systems are of two types
–
1.Reprogrammable – e.g.:- Microcomputers
(general purpose)
2.Embedded – e.g. :- Xerox machine, Washing
machine, Traffic light controller
Microcomputers
Input Output
µP Bus
(CPU)
Memory
SYSTEM BUS
This is comprised of the control bus, data bus and address bus. It is used for
connections between the processor, memory and peripherals, and transferral
of data between the various parts.
Microcomputer system consists of four sections –
1.Microprocessor (CPU)
2.Memory (ROM and RAM)
3.Input
4.Output
1. The Microprocessor
4. Output
Output unit transfers the processed data from the
microprocessor to the output devices such as LED, CRTs, Video
Monitor, Line printers, LCD projectors etc.
INTEL 8085
40 pin dual – in - line package (DIP).
Pin 1 & 2
Crystal at a required frequency (500 KHz to 3.125 MHz)
Pin 3
When we switch on the system, the peripheral chips are being reset.
Pin 4
SOD converts Acc data in to a Serial data stream
Pins 12 to 19 & 21 to 28
Pins 12 to 18 carry the lower order 8 address bits or 8 data bits.Pins 21 to 28
contain the rest of the address bus.
Pin 20
Ground
Pin 30
The Memory Address Register (MAR) in each memory chip is called Address
latch. It stores the address from the Address bus and Address data bus. The falling edge
of ALE signal loads the address on the Address bus and Address data bus in to the MAR
of the memory chips.
Pin 36
If = 0, the processor resets the whole system and sends a high RESET OUT to
pin 3.
Pin 35
Some of the peripheral devices are unable to run at the same speed at the 8085,
because of the low speed operation. If the device is not ready, the device will send a low
READY bit to the 8085. Then 8085 is in WAIT state.
Pin 37
Carries a clock out signal which obtained from the on-chip oscillator. This
signal goes to the peripheral chips to synchronize their timings.
Pin 38, 39
In order to speedup data transfer between memory and a peripheral device, the
processor need not be involved. The solution for this is direct memory access operation,
with HOLD and HLDA control signals.
FUNCTIONAL BLOCK DIAGRAM OF 8085
INTA
RST 6.5 TRAP SID SOD
INTR RST 5.5 RST 7.5
A
Temp. Flag Instruct B (8) C (8)
ACCUMU
LATOR reg. register ion
GPR
register
D (8) E (8)
REGISTER ARRAY
(ACC)
(8) (8) (5) (8)
H (8) L (8)
(16)
STACK POINTER
Arithmetic Instruction
Logic Unit decoder &
(ALU) Machine
cycle PROGRAM COUNTER (16)
(8) encoding
INCREMENTER / DECREMENTER
X2 X1 GND +5V
ADDRESS LATCH (16)
Serial I/O control : The mode of transmission from the I/O devices is either in serial
form or in parallel form. In certain cases, I/O devices operate with serial data rather
than parallel. Hence before the computer operation, the serial data stream from an
output device must be converted to 8 bit parallel data. the SID input is where serial
data enters and the SOD output is where the serial data leaves.
Timing and Control : It is a part of CPU. It generates timing and control signals for
the execution of instructions. The control signal of this unit controls dataflow
between CPU and peripherals. It controls the entire operations of the Microprocessor
and the peripherals connected to it.
Registers in the 8085 and their functions
7 6 5 4 3 2 1 0 BIT NO.
S Z X AC X P X CY STATUS FLAGS
UNDEFINED BITS
a)Zero (Z) : If a result of an instruction has a value zero, this flag is set, otherwise it is
reset.
b)Sign (S) : If the MSB of the result of the operation has value 1, this flag is set, otherwise
it is reset.
c)Carry (CY) : If the instruction resulted in a carry (from addition) or a borrow (from
either the subtraction or comparison), out of the higher order bit, this flag is set,
otherwise it is reset.
d)Auxiliary carry (AC) : This flag holds carry out of bit three to bit four resulting from
the execution of an arithmetic operation, it can set or reset.
e)Parity (P) : This flag is set, when the result of the operation contains even number of 1s
and is reset when there is odd number of 1s.
Bus means a group of lines on which bit appear in parallel at a time.
1. DATA BUS
Unidirectional bus
3. ADDRESS BUS
µP
I/O Input devices
ROM RAM
Ports
Output devices
D0 – D7
To demultiplex the address / data lines (of the µP), the processor provides a signal
called ALE (Address Latch Enable). The ALE is asserted High and then Low by the processor at
the beginning of every machine cycle. At the same time, the low byte address is given out
through AD0 – AD7 lines. The demultiplexing of address / data lines using 8 bit D – latch
74LS373 is shown in figure.
The ALE is connected to the Enable pin EN of an external 8 bit Latch. When ALE is
asserted high and then low, the addresses are latched in to the output lines of the latch. It holds
the low byte of the address until next mission cycle. After latching the address, the AD0 - AD7
lines are free for data transfer. The first T - state of every machine cycle is used for address
latching in 8085 and the remaining T – states are used for reading or writing operation.
GENERATNG CONTROL SIGNALS
The RD signal is asserted low by the 8085 during a memory or I/O READ operation.
Similarly the WR pin signal is asserted low during a memory or I/O WRITE operation.
The IO/M, S0, S1 are output by the 8085 during its internal operations, which can be
interpreted as shown in the table below.
0 0 1 Memory WRITE
0 1 0 Memory READ
1 0 1 I/O WRITE
1 1 0 I/O READ
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
The READY input can be used by the slower external
devices for obtaining extra time in order to communicate with
the 8085. The READY is made low to provide WAIT state
Clock periods in the machine cycle.
The HOLD and HLDA signals are used for the DMA
type of data transfer. The DMA controller place a HIGH on
HOLD pin in order to take control of the system bus. The
HOLD function is acknowledged by the 8085 by placing a
HIGH output on the HLDA pin.
ARCHITECTURE OF 8085
Functional Block diagram
Description of
ALU
Timing and control Unit
Instruction Register and Decoder
Register Array
Interrupt control
Serial I/O Control
Description of
ALU
Flag Register
SP
PC
DECODING AND EXECUTING AN INSTRUCTION
Once the opcode is known, the execution cycle can occur. However, there are generally
four groups of different actions that can occur:
qProcessing of data, possibly involving the use of the arithmetic and logic unit.
qA control operation, in order to change the sequence of subsequent operations. These can
possibly be conditional, based on the values stored at that point within the flag register.
µP
Internal Data Bus
Memory
3E F800
Data Bus 05 F801
F802
3E
General F803
Instruction Purpose F804
ALU Decoder reg. F805
Address Bus
BC
DE F800
RD
Control
Logic IO/M
EXAMPLES OF SOME MNEMONICS
Mnemonic Description
ADD Adds to data values using the ALU, and returns the result to
the accumulator
Reference: