VHDL --- CODE

[V HDL [Hardware Description Language]]

V --- VHSIC [ Very High Speed Integrated Circuit]

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• Why VHDL is referred as CODE and NOT as Program

• Program ---> Sequential ---> On Computer

• Code ---> Concurrent [ Parallel] ---> Digital BOARD

What about HDL codes generated from

cross compliers ?

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 VHDL CODE

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 VHDL Design Flow

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 Library

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 ieee library
Various Packages..

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 Entity

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• Modes
• IN, OUT, INOUT

• Signal Types – BIT,BIT_VECTOR, STD_LOGIC,

STD_LOGIC_VECTOR , INTEGER

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 ARCHITECTURE
Describes how the circuit should behave / function

Optional [ declaration] – signal, constant

Code --- after BEGIN

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 DATA TYPES IN VHDL
Pre defined and the User defined

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 Data Types
• Pre defined types

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 `

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 Where U stands for UNRESOLVED

STD_LOGIC is a subset of STD_ULOGIC,

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• Resolved signal can be driven by multiple
drivers
• A resolved type permits multiple drivers on a
signal.
• An unresolved type (like std_ulogic) does not
permit multiple drivers.
• This is detected during analysis and will result
in an error.
• A driver for a signal exists for each signal
assignment
• When one driver should applies a strong value
(e.g. '0' or '1') while the others apply a weak
value (amongst others 'L', 'H' and 'Z').
• The resolution function determines the actual
value that will be assigned to the signal.
• A strong value will win from a weak value.
• So if there are two drivers driving '1' and 'Z', the
resulting value will be '1'.
• A '0' and a '1' will result in an 'X'.
• Resolution table
Types of Architectures
 IDENTIFIERS, DATA OBJECTS AND DATA TYPES

VHDL

Data
Identifiers objects Data types

constants Signals Variables

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 Identifiers
It is about how to create names

• Used to represent an object (constant, signal or

variable)

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 Rules for Identifiers
• Names for users to identify data objects:
signals, variables etc.
• First character must be a letter
• last character cannot be an underscore
• Not case sensitive
• Two connected underscores are not allowed
• Examples of identifiers: a, b, c, axy, clk ...

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Data objects

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 Data objects
• Constant
• Signals VHDL
• variables
Data
Identifiers objects Data types

Constants Signals Variables

(Global) (Global) (Local)

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 Data objects: 3 different objects
• 1 Constants: hold values that cannot be changed within a
design.
– e.g. constant width: integer :=8
• 2 Signals: to represent wire connections
– e.g. signal count: bit_vector (3 downto 0)
– -- count means 4 wires; they are count(3),count(2), count(1),
count(0).
• 3 Variables: internal representation used by programmers;
do not exist physically.

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Syntax to create data objects

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 Constants with initialized values
• constant CONST_NAME: <type_spec> := <value>;
• -- Examples:
• constant CONST_NAME: BOOLEAN := TRUE;
• constant CONST_NAME: INTEGER := 31;
• constant CONST_NAME: BIT_VECTOR (3 downto 0) := "0000";
• constant CONST_NAME: STD_LOGIC := 'Z';
• constant CONST_NAME: STD_LOGIC_VECTOR (3 downto 0) := "0-0-"; --
‘-’ is don’t care

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 Signals with initialized values

• signal sig_NAME: type_name := init. Value;

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 Variables with initialized values
• variable V_NAME: type_name := init. Value;
• -- examples
– variable v1_bool : BOOLEAN:= TRUE;
– variable val_int1: INTEGER:=135;
– variable vv2_bit: BIT; -- no initialized value

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 Signal and variable assignments
• SIG_NAME <= <expression>;
• VAR_NAME := <expression>;

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 Different data types
Enumeration Chapter2
:
Red, blue
standard Data
Boolean:
logic: Identifiers objects Data types
“TRUE”,
•
Resolved,
Unresolved
”FALSE”

Constants Signals Variables

(Global) (Global) (Local)

Float: Data Bit:

0.124 0,1
types

Integer: Character
13234,23 ‘a’,’b’

String:
“text”

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Integers
BINARY
 Examples of some common types
• Type BOOLEAN is (FALSE, TRUE)
• Type bit is (‘0’ ,’1’);
• Type character is (-- ascii string)
• Type INTEGER is range of integer numbers
• Type REAL is range of real numbers

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 Boolean, Bit Types
• Boolean (true/false), character, integer, real,
string, these types have their usual meanings.
In addition, VHDL has the types: bit,
bit_vector,
• The type “bit” can have a value of '0' or '1'. A
bit_vector is an array of bits.

VHDL 2. Identifiers, data objects and data

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types ver.5a
User defined Data Types
• TYPE
• SubTYPE
• Enumerated
• Arrays
• Records
• TYPE
 Enumeration types:
• An enumeration type is defined by listing
(enumerating) all possible values
• Examples:
• Type COLOR is (BLUE, GREEN, YELLOW, RED);
• Type MY_LOGIC is (’0’, ’1’, ’U’, ’Z’);
• -- then MY_LOGIC can be one of the 4 values

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 Enumerated types

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 Color -> has four states

Value Color STATE

00 RED 1
01 GREEEN 2
10 BLUE 3
11 WHITE 4

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• SUBTYPE
• TYPE with a CONSTRAIN

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 Attributes
• The purpose of attributes is to give VHDL more
flexibility and also the construction of generic
codes.

1. Data Attribute
2. Signal Attribute
d refers to the signal
Examples
 Conversion Function available with
std_logic_arith package of ieee library

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 Summary of data types

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